Professional Documents
Culture Documents
Schedule
Xputer Lab
University of Kaiserslautern
time
08.30 10.00 10.00 10.30 10.30 12.00 12.00 14.00 coffee break
slot
Reconfigurable Computing (RC) Stream-based Computing for RC lunch break
14.00 15.30
15.30 16.00 16.00 17.30
Resources for RC
coffee break FPGAs: recent developments 2
http://www.fpl.uni-kl.de
2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Configware market taking off for mainstream FPGA-based designs more complex, even SoC No design productivity and quality without good configware libraries (soft IP cores) from various application areas. Growing no. of independent configware houses (soft IP core vendors) and design services AllianceCORE & Reference Design Alliance Currently the top FPGA vendors are the key innovators and meet most configware demand.
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Select EDA quality / productivity, not FPGA architectures EDA often has massive software quality problems Customer: highest priority EDA center of excellence
collecting EDA expertise and EDA user experience to assemble best possible tool environments for optimum support design teams to cope with interoperability problems to keep track with the EDA scene as a rapidly moving target
being fabless, FPGA vendors spend most qualified manpower in development of EDA, IP cores, applications , support Xilinx and Altera are morphing into EDA companies. 7 http://www.fpl.uni-kl.de 2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
OS for FPGAs
separate EDA software market, comparable to the compiler / OS market in computers, Cadence, Mentor, Synopsys just jumped in. < 5% Xilinx / Altera income from EDA SW
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Full design flow from Cadence, Mentor, & Synopsys Xilinx Software AllianceEDA Program:
Alliance Series Development System. Foundation Series Development Systems. Xilinx Foundation Series ISE (Integrated Synthesis Environment) free WebPOWERED SW w. WebFitter & WebPACK-ISE StateCAD XE and HDL Bencher Foundation Base Express Foundation ISE Base Express
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
ModelSim Xilinx Edition (ModelSim XE) Forge Compiler Modular Design Chipscope ILA
Xputer Lab
University of Kaiserslautern
Altera EDA
Altera was founded in June 1983 EDA: synthesis, place & route, and, verification Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families MAX+PLUS II: FLEX, ACEX & MAX families Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. Mentor: only EDA vendor w. complete design environment f. APEX II incl. IP, design capture, simulation, synthesis, and h/s coverification Configware: Altera offers over a hundred IP cores Third party IP core design services and consultants
2001, reiner@hartenstein.de
11
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Cadence
FPGA Designer: top-down FPGA design system, high-level mapping, architecture-specific optimization, Verilog,VHDL, schematic-level design entry. Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer FPGAs simulated by themselves using Cadence's VerilogXL or Leapfrog VHDL simulators and simulated w. rest of the system design w. Logic Workbench board/system verification envment. Libraries for the leading FPGA manufacturers.
2001, reiner@hartenstein.de
12
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Mentor Graphics
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Synopsys
FPGA Compiler II
14
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
15
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Lattice 15%
Actel 6%
Xilinx 42%
Altera 37%
$3.7 Bio
2001, reiner@hartenstein.de
16
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Meanwhile,
Xilinx acquired Philips' MOS PLD business, Lattice purchased Vantis. .
2001, reiner@hartenstein.de
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
[Dataquest] PLD market > $7 billion by 2003. fastest growing segment of semiconductor market. IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs FPGAs are going into every type of application.
2001, reiner@hartenstein.de
18
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
19
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Xilinx
fabless FPGA semi vendor, San Jose, Ca, founded 1984 key patents on FPGAs (expiring in a few years) Fortune 2001: No. 14 Best Company to work for in (intel: no. 42, hp no. 64, TI no. 65). DARPA grant (Nov99) to develop Jbits API tools for internet reconfigurable / upgradable logic (w. VT) Less brilliant early/mid 90ies (president Curt Wozniak): 1995 market share from 84% down to 62% [Dataquest]
As designs get larger, Xilinx losed its advantage (bugfixes did not require to burn new chips)
meanwhile, weeks of expensive debug time needed
2001, reiner@hartenstein.de
20
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Xilinx Flexware
for low-cost, high volume applications as ASIC replacements Multiple I/O standards, on-chip block RAM, digital delay lock loops eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers rapid development, longer system life, robust field upgradability support In-System Programming (ISP), in-board debugging, test during manufacturing, field upgrades, full JTAG compliant interface
CoolRunner: low power, high speed/density, standby mode. Military & Aerospace: QPRO high-reliability QML certified Configuration Storage Devices
2001, reiner@hartenstein.de
21
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Altera Flexware
Newer families: APEX 20KE, APEX 20KC, APEX II, MAX 7000B, ACEX 1K, Excalibur, Mercury families.
Apex EP20K1500E (0.18-), up to 2.4 mio system gates, APEX II (all-copper 0.13-) f. data path applications, supports many I/O standards. 1-Gbps True-LVDS performance
Altera mainstream: MAX 7000A, 3000A; FLEX 6000, 10KA, 10KE; APEX 20K families.
Mature and other : Classic, MAX 7000, 7000S, 9000; FLEX 8000, 10K families.
2001, reiner@hartenstein.de
22
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Triscend CSoC
[Kean]
Configurable system logic
ARM
Digital Filter
Display Interface
Viterbi
A/D Interface
CSI Socket
Configurable System Interconnect (CSI) Bus
Memory
2001, reiner@hartenstein.de
23
http://www.fpl.uni-kl.de
2001, reiner@hartenstein.de
Configware Market FPGA Market Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved
24
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
[ la S. Guccione]
Schematics/
HDL
Netlister
Netlist
Route
Place and
Bitstream
HLL
Compiler
2001, reiner@hartenstein.de
25
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
[ la S. Guccione]
HLL
Schematics/ Place and
Compiler
HDL
Netlister
Netlist
Route
. .
Bitstream
User Code
Compiler
Executable
2001, reiner@hartenstein.de
26
http://www.fpl.uni-kl.de
University of Kaiserslautern
Overcome traditional co-processing design Xputer Lab separate flow -> JBits Design Flow
JBits API User Java Code
[ la S. Guccione]
Schematics/
HDL
Netlister
Netlist
Place and
Route
. .
Java Compiler
Executable
Bitstream
User Code
Compiler
Executable
2001, reiner@hartenstein.de
27
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLL
Compiler
Compiler
2001, reiner@hartenstein.de
28
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
supports Run-Time Reconfiguration (RTR), a key enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as remote patching for upgrading, remote debugging, and remote repair by reconfiguration - even over the internet.
2001, reiner@hartenstein.de
29
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
30
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
on-board microprocessor CPU is available anyhow - even along with a little RTOS use this CPU for configuration management
HLL
Compiler
2001, reiner@hartenstein.de
31
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLL
Compiler
FPGA core
HLL
Compiler
2001, reiner@hartenstein.de
32
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Converging factors make RTR based system design viable 1) million gate FPGA devices and co-processing with standard microprocessors are commonplace direct implementation of complex algorithms in FPGAs. This alone has already revolutionized FPGA design. JBits 2) new tools like Xilinx Jbits API software tool suite directly support coprocessing and RTR. User
Java Code
Java Compiler
Executable
2001, reiner@hartenstein.de
33
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
RTR
divides application into a series of sequentially executed stages, each implemented as a separate execution module. Partial RTR partitions these stages into finer-grain sub-modules to be swapped in as needed. Without RTR, all conf. platforms just ASIC emulators. needs a new kind of application development environments. directly support development and debugging of RTR appl. essential for the advancement of configurable computing will also heavily influence the future system organization Xilinx, VT, BYU work on run-time kernels, run-time support, RTR debugging tools and other associated tools. smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces.
2001, reiner@hartenstein.de
34
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Run-time Mapping
run-time reconfigurable are: Xilinx VIRTEX FPGA family RAs being part of Chameleon CS2000 series systems Using such devices changes many of the basic assumptions in the HW/SW co-design process: host/RL interaction is dynamic, needs a tiny OS like eBIOS, also to organize RL reconfiguration under host control typical goal is minimization of reconfiguration latency (especially important in communication processors), to hide configuration loading latency, and, Scheduling to find best schedule for eBIOS calls (C~side). 35
http://www.fpl.uni-kl.de
2001, reiner@hartenstein.de
2001, reiner@hartenstein.de
Configware Market FPGA Market Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved
36
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
ASIC emulation / Rapid Prototyping: to replace simulation Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor) from rack to board to chip (from other vendors, e. g. Virtex and VirtexE family (emulate up to 3 million gates) Easy configuration using SmartMedia FLASH cards
37
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
38
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
"Evolvable Hardware" (EH), "Evolutionary Methods" (EM), digital DANN, "Darwinistic Methods", and biologically inspired electronic systems
new research area, also a new application area of FPGAs
Xputer Lab
University of Kaiserslautern
Shake-out phenomena expected, like in the past with Artificial Intelligence should be considered as a specialized EDA scene, focusing on theoretical issues. Genetic algorithms suck - often replacable by more efficient ones from EDA It is recommendable to set-up an interwoven competence in both scenes, EM scene and the highly commercialized EDA scene EH should be done by EDA people, rather than EM freaks.
2001, reiner@hartenstein.de
40
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
41
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
BRASS (1)
The Pleiades Project, Prof. Jan Rabaey, ultra-low power highperformance multimedia computing through reconfiguration of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right granularity, parallellism, pipelining, dynamic voltage scaling. Garp integrates processor and FPGA; dev. in parallel w. compiler - software compile techniques (VLIW SW pipelining): simple pipelining schema f. broad class of loops.
SCORE, a stream-based computation model - a unifying computational model. Fast Mapping for Datapaths: by a treeparsing compiler tool for datapath module mapping 42 http://www.fpl.uni-kl.de 2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
BRASS (2)
HSRA. new FPGA (& related tools) supports pipelining, w. retiming capable CLB architecture, implemented in a 0.4um DRAM process supporting 250MHz operation OOCG. Object Oriented Circuit-Generators in Java MESCAL (GSRC), the goal is: to provide a programmer's model and software development environment for efficient implementation of an interesting set of applications onto a family of fully-programmable architectures / microarchitectures.
2001, reiner@hartenstein.de
43
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread reconfigurable computing, by a unifying computational model.
Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath module mapping ." Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity."
2001, reiner@hartenstein.de
44
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Remark: The DPSS (Data Path Synthesis System) using tree covering simultanous datapath placement and routing has been published in 1995 by Rainer Kress Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Brodersons radical rethink of the ASIC design flow aimed at shortening design time, relying on stream-based DPU arrays. [published in 2000] Remark: the KressArray, a scalable rDPU array [1995] is stream-based
2001, reiner@hartenstein.de
45
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Hardware/Compiler techniques for improving memory performance of media and stream-based processing Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming applications System-on-a-chip architectures for media & stream processors Hardware/Software Co-Design of media and stream processors and others ....
2001, reiner@hartenstein.de
46
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting a radical rethink of the ASIC design flow aimed at shortening design time. Relying on stream-based DPU arrays (not rDPU and related EDA tools. Davis: ... 50x decrease in power requ. over typical TI C64X design.
New design flow to break up the highly iterative EDA process, allowing designers to spend more time defining the device and far less time implementing it in silicon. ... developers to start by creating data flow graphs rather than C code,
It is stream-based computing by DPU array (hardwired DPA) For hardwired and reconfigurable DPU array and rDPU array
2001, reiner@hartenstein.de
47
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs no activities seen other than YAFA (yet another FPGA application) UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P algorithms. 9 projects, mult. sponsors under California MICRO Program Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs, a new routing architecture, architecture-aware CAD, IP-aware SPS compiler USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable computing: MAARC project, DRIVE project and Efficient SelfReconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation o scalable multiprocessors. DEFACTO proj.: compilation - architecture-independent at all levels MIT. MATRIX web pages removed `99. RAW project: a conglomerate VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w Prof. Brad Hutchings, BYU on programming approaches for RTR System BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware 48 http://www.fpl.uni-kl.de Description Language) and compilation of JHDL sources into FPGAs. 2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
The group has dev. Transmogrifier C, a C compiler creating netlist for Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.
Founder of Right Track CAD Corporation acquired by Altera in 1999 Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff Arnold) Project Streams-C: programming FPGAs from C sources. Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins, methods for MPEG-4 like multimedia applications on dynamically reconfigurable platforms, & on reconf. instruction set processors. University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. synthesis for future mobile communication systems & synthesis w. distributed internet-based CAD methods, partitioning co-compilers
2001, reiner@hartenstein.de
49
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
50
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
51
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2. An FPGA is pre-fabricated
2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
Testing Yield Cross Talk Noise Leakage Clock Tree Design Horrible very deep submicron effects we dont even know about yet
53
http://www.fpl.uni-kl.de
2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
Make Too Many You Pay holding costs Make Too Few Competitor gets the Sale
2001, reiner@hartenstein.de
54
[Jonathan Rose]
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Instant Fabrication
Get to Market Fast Fix em quick
2001, reiner@hartenstein.de
55
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
9 Times Out of 10
You make can the thing fast by breaking it into multiple parallel slower pieces
2001, reiner@hartenstein.de
56
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
[Jonathan Rose] 1. Still Have to Make the Chip 2. Need Two Sets of Software to Build It
Xputer Lab
University of Kaiserslautern
[Jonathan Rose]
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
59
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
60
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Dual-Port RAM
Single-Port RAM
[Jonathan Rose]
2001, reiner@hartenstein.de
61 Available Today!
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLL
Compiler
soft CPU
FPGA
2001, reiner@hartenstein.de
62
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Nios
Nios 50 MHz Nios gr1040
Altera Mercury
Altera 22 D-MIPS Altera Mercury
REGIS Reliance-1
1Popcorn-1 Acorn-1
8 bit CISC
gr1050
My80
32-bit
i8080A FLEX10K30 or EPF6016
YARD-1A xr16
DSPuva16
16 bit DSP
Spartan-II
2001, reiner@hartenstein.de
63
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
64
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
CPU core Reliance 1 PopCorn 1 Acorn 1 16-bit DSP Free-6502 DLX DLX2
Description 12bit DSP and peripherals small 8 bit CISC small 8 bit CISC A 16-bit Harvard DSP with 5 pipeline stages. 6502 compatible core Generic 32-bit RISC CPU Generic 32-bit RISC CPU
GL85
AMD 2901 AMD 2910 i8051 i8051
i8085 clone
AMD 2901 4-bit slice AMD 2910 bit slice 8-bit micro-controller another i8051 clone
VHDL
VHDL VHDL VHDL VHDL Synopsys Mentor Graphics
http://www.fpl.uni-kl.de
2001, reiner@hartenstein.de
65
Xputer Lab
University of Kaiserslautern
UCSC: 1990!
Mraldalen University, Eskilstuna, Sweden Chalmers University, Gteborg, Sweden Cornell University Gray Research Georgia Tech Hiroshima City University, Japan
2001, reiner@hartenstein.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
67
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
[ la S. Guccione]
2001, reiner@hartenstein.de
68
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Performance 1000
100
10 1 1980
CPU
DRAM
1990 2000 DRAM 7%/yr..
[ la S. Guccione]
2001, reiner@hartenstein.de
69
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
miscellanous
HLL
Compiler soft CPU
Memory
[ la S. Guccione]
2001, reiner@hartenstein.de
70
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
miscellanous
HLL
Compiler
CPU
Memory
[ la S. Guccione]
2001, reiner@hartenstein.de
71
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
>> HLLs
Configware Market FPGA Market Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved
2001, reiner@hartenstein.de
72
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLLs for Hardware Design vs. System Design vs. RTR System Design
HLL
System Design
Compiler
HLL
[ la S. Guccione]
2001, reiner@hartenstein.de
Compiler
73
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLLs for Hardware Design vs. System Design vs. RTR System Design
Compiler
HLL
HLL
System Design
Compiler
HLL
[ la S. Guccione]
2001, reiner@hartenstein.de
Compiler
74
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLL
Compiler
FPGA core
HLL
[ la S. Guccione]
2001, reiner@hartenstein.de
Compiler
75
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Jbit Environment
RTP Core Library JBits API User Code BoardScope Debugger
[ la S. Guccione]
JRoute API
XHWIF
TCP/IP
Device Simulator
2001, reiner@hartenstein.de
76
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
HLLs for Hardware Design vs. System Design vs. RTR System Design
HLL
Compiler
HLL
System Design [ la S. Guccione]
2001, reiner@hartenstein.de
Compiler
77
http://www.fpl.uni-kl.de
Memory core
Compiler
soft CPU
FPGA
78
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
79
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
2001, reiner@hartenstein.de
80
http://www.fpl.uni-kl.de
Schedule
Xputer Lab
University of Kaiserslautern
10.30 12.00
12.00 14.00 14.00 15.30 15.30 16.00 16.00 17.30
17.30
2001, reiner@hartenstein.de