-PIPELINE ADC-Presented by Prashant Chaudhari -Guided by Prof.G.R.

Phulay

Contents Introduction Literature Reviews System Development Performance Analysis Conclusions

Introduction
Need of the system
A single ADC model to meet requirements for multiple applications Implementation in the digital domain for a lower cost, lower power consumption, higher yield, and higher reconfigurability

Objective
Provide a background on pipeline adcs Introduce a novel front-end capshare technique that saves power in the front-end S/H Show the theoretically power savings of the technique through a design comparison

LITERATURE REVIEWS
Basic types of ADCs
Flash type of ADC
Successive approximation (SAR) type ADC Sigma- Delta convertor
ARCHITECTURE LATENCY SPEED ACCURACY AREA

Flash
Delta-Sigma Successive Approximation (SAR) Pipeline

No
Yes Yes Yes

High
Low Low Medium

Low
High Medium-High Medium-High

High
Medium Low Medium

ONE-STAGE PIPELINE
Basic structure of 1 stage pipeline ADC

System Developments
PIPELINE ADC BUILDING BLOCKS AND DESIGN METHODOLOGY
Opamp design Building blocks Design procedure Capacitor-sharing pipeline

OPAMP design
Gain:

Bandwidth:

Output voltage swing

BUILDING BLOCKS
1) Sub-ADC:

2) Sample And Hold:

Performance analysis
REGULAR VERSUS CAPSHARE ADC
1) Regular pipeline ADC with a flip-around MDAC in the first stage:

2) Pipeline ADC with capacitor-sharing front-end:

POWER COMPARISON And ANALYSIS

SNDR and SNR at fin = 61/128 fS
Sim 1 2 3 4 5 6 7 Pipeline Type Regular Capshare Regular Capshare Regular Capshare Regular fS 2 2 2 2 20 20 20 Thermal Noise No No Yes Yes No No Yes SNDR[dB] 62.1 60.9 59.0 59.2 52.2 54.1 51.2 SNR[dB] 62.5 61.4 59.4 59.3 61.4 62.6 58.2 ENOB[bits] 10 9.82 9.51 9.54 8.37 8.70 8.21

Experimental results of capshare ADC measured at different fin and fS

Measurement

Fs [MHz]

Fin [MHz]

SNDR [dB]

SNR [dB]

ENOB [bits]

Panalog [mW]

Pdigital [W]

FOM [pJ/step]

1
2 3 4 5 6 7 8 9 10

0.4
5 10 14 20 20 20 20 20 24

0.19
2.38 4.77 6.67 2.03 4.84 9.53 12.0 13.6 11.4

53.9
53.8 53.8 53.1 53.0 53.1 53.0 51.4 51.0 51.9

54.2
54.3 54.4 53.7 53.9 54.4 54.1 53.5 52.6 53.6

8.67
8.65 8.65 8.52 8.51 8.53 8.51 8.25 8.18 8.33

4.06
4.21 4.25 4.28 4.26 4.28 4.30 4.32 4.31 4.34

8.64
106 212 297 422 422 423 421 423 507

26.2
2.25 1.17 0.93 3.15 1.32 0.68 0.65 0.60 0.66

CONCLUSIONS
A novel front-end capacitor-sharing technique

that significantly reduces the power consumption

in the front-end S/H A comparison was conducted between a capshare pipeline ADC and a regular pipeline ADC The front-end capshare stage caused the

dynamic range to drop below the thermal noise

level

THANK YOU