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Basic idea, saturating counter, BHT, BTB, return address prediction, correlating prediction
2. Predict branch/jump target address (for taken 3. Speculatively execute instructions along the
predicted path
2
What to predict:
Current predicted PC Past branch history (direction and target) Conditional branch inst: branch direction and target address Jump inst: target address Procedure call/return: target address
PC
pred_PC
IM
Predictors
PC & Inst
Target address known at decoding, and not match Flush fetch stage Wrong branch direction or target address not match Flush the whole pipeline
predictors
Feedbacks: Any time a mis-prediction is detected At a branchs commit (at EXE: called speculative update)
WB
COMMIT
4
Static prediction: compilers decide the direction Dynamic prediction: hardware decides the direction using dynamic information
1. 2. 3. 4. 5.
1-bit Branch-Prediction Buffer 2-bit Branch-Prediction Buffer Correlating Branch Prediction Buffer Tournament Branch Predictor and more
PC
state
3. Feedback T/NT
1-bit prediction
T Predict Taken NT
Feedback
NT T
Predict Taken
Branch address
2k
Prediction
11 01
NT
T
T NT T NT
10
Predict Taken
00
NT
Blue: stop, not taken Gray: go, taken Adds hysteresis to decision making process
Note: must check for branch match now, since cant use wrong branch address
Predicted PC
Extra Yes: instruction is prediction state branch and use bits predicted PC as next PC
10
Many callers, one callee Jump to multiple return addresses from a single address (no PC-target correlation)
SPEC89 85% such branches for procedure return Since stack discipline for procedures, save return address in small buffer that acts like a stack: 8 to 16 entries has small miss rate
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Correlating Branches
Code example showing the potential
If (d==0) d=1; If (d==1)
Assemble code
BNEZ R1, L1 DADDIU R1,R0,#1 L1: DADDIU R3,R1,#-1 BNEZ R3, L2 L2:
Prediction
13
Prediction
14
18%
16%
14%
4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT
11%
12%
10%
8%
6% 6% 6% 5% 4%
6%
5%
4%
2%
1% 0%
1%
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16
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