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Introduction
The three factors together with the creative minds of the times have yielded the most prominent and outstanding designs in the direction taken by research in a field is a function of
the prevailing design philosophy the requirements imposed on that field by other disciplines the shortcomings of existing designs/systems.
Basic "memory" elements-(a) A NAND gate-based SR latch with its truth table. The S and R inputs are active low and represented as Sb and Rb, respectively (b) A NAND gate- based JK latch derived from the SR latch in Fig.a with its truth table. The J and K inputs are active high.
(c) A T (toggle) latch derived from the JK latch with its truth table (d) A D (delay) latch derived from the JK latch with its truth table.
Because latches and flip-flops in synchronous circuits were used mainly as delay elements to buffer input, the words latch and flip-flop became synonymous with the D latch and flip-flop.
(a) A fully static clocked SR latch with S and R as active high inputs
Contd.,
A large decrease in the number of transistors is possible by using the bi- directionality feature of the MOS transistorthe pass transistor design style (Fig.5.5a). The pass transistor version of the D flip-flop requires merely 12 transistors. As pass transistors suffer from lack of full swingthe logic 1 level transferred is degraded (VDD - Vtn). This deficiency can be overcome by using transmission gates (Fig 5.5b). As a result of bidirectionality, either a pass transistor or a transmission gate does not isolate the input from the output.
Contd.,
INV2 is a weak transistor made using small gain p- and n-devices. Because of the bidirectionality of the transmission gate, the setup time of this latch would be high given that INV2 would have to drive the parasitic capacitance at the input. Also if the input is being driven by another logic circuit, and the clock is a high, the feedback from the latch could prevent the input from switching or, at the least, impede its switching. => Fig.5.5 & 5.6, a reduction in area is generally obtained by making appropriate tradeoffs with either speed or power or robustness.
Area was the main object of concern. Uses 6 transistors, requires 2 complementary clocks. problem with providing 2 complementary clocks is the difficulty of routing near-perfect overlapping clocks. This spurred the idea of twoand four-phase clocks.
Contd.,
Fig.a. shows a two-phase clock with two phases 1 and 2, and Figure 5.8b shows a four-phase clock with phases 1, 2, 3 & 4. => clock and clockb of the flip-flop can be replaced with 1 & 2, respectively, thereby producing a flipflop free from feed through problems and race conditions. When the two-phase clock is used in static circuits, the time t12 (the delay between 1 being high and 2 being high) must be as small as possible to ensure that the feedback action comes into operation as soon as the input is switched off. However, t12 must be made as large as possible to eliminate feed through. These two competing demands place tight constraints on the designers.
Contd.,
1 & 3 are used for precharging. Because 2 & 3 are non-overlapping, the evaluation of the first stage occurs before the second stage is precharged. Suffers from charge-sharing problems between nodes X and Y. The way to avoid this problem is to ensure that 2 is on when node X is being precharged. This practice ensures that node Y is charged from VDD rather than by charge sharing with node X. Similarly, 4 is on when node Y is precharged. To ensure that no skew develops between different clock phases of these two- and four-phase clocks, each phase must be routed in an identical manner to the others. 2 parallel long wires tend to suffer from crosstalk. For chip's operation speed >100 MHz, it is difficult to generate nonoverlapping clocks and control the clock skew properly in a VLSI chip as a result of statistical variations of components in the clock distribution path. The difficulty involved in routing so many clock phases rekindled interest in a single-phase clock and single-phase structures.
The first consistent framework for pipelining came with the NORA (No- RAce) technique.
The NORA technique evolved from the Domino logic where the outputs of all cascaded stages go to logic 0 on precharge (Fig.5.11). During the evaluation period, the stages are successively evaluated much like a row of dominos falling. In Domino logic, all logic inputs are present in the n-logic blocks; however, in the NORA logic, they are placed alternately between n- and p-logic blocks. One n-logic block combined with another p-logic block and a C2MOS latch form a separate section.
Contd.,
Contd.,
Based on the clock phase used to precharge the section, these sections are divided into two types the -sections, shown in Fig.5.12a, which are precharged when is a low, and b sections, illustrated in Fig.5.12(b), which are precharged when b is low. When the logic in the -section is being precharged, the C2MOS latch causes the data at the output to be at hold. At the same time, the b section is evaluating. => if the sections and the b sections are interleaved, data is transferred to the output in a pipelined fashion.
While the NORA provides a consistent framework for fast pipelines, some conditions are placed on the logic as follows: 1. The number of static inversions between two C2MOS latches should be even (in the absence of dynamic gates). 2. The number of static inversions between a C2MOS latch and a dynamic gate should be even.
The C2MOS functionality could be achieved without using a two-phase clock; hence, the concept of true single-phase clock (TSPC) latches and flip-flops.
Contd.,
The TSPC did away with the rules imposed on logic by the NORA technique. Fig.5.13 shows the basic stages in TSPC logic.
Contd.,
Fig.5.14 shows a negative edge-triggered TSPC based flip-flop.
This flip-flop contains 9 transistors compared to the eight used in C2MOS. However, because routing a two- to four-phase clock was difficult, a singlephase solution was most welcome. Wave pipelining, removes the need for latches and flip-flops and yields the greatest possible throughput - the pipelining concept to the extreme, using logic element delays as the delay elements of the circuit.
Contd.,
In single edgetriggered flipflops, one edge of the clock is always redundant. In an effort to reduce unnecessary power dissipation, double edgetriggered designs are gaining prominence.
Contd.,
Most double edge-triggered flip- flops constructed to date are composed of two single edge-triggered sections placed in parallel with each other (Sections A and B) followed by some combining logic to multiplex the output signals. A double edge-triggered flip-flop can handle a data rate twice that of a single edge-triggered flip-flop. This change allows these flip-flops to be clocked at half the frequency, thus reducing the power dissipation by half. Double edge-triggered flip-flops require almost twice the area as single edgetriggered flip-flops. This fact is the most prominent pointer toward a shift in designer priorities from small silicon area to low power. Considering the tremendous power dissipation due to the clock, researchers have started exploring other design paradigms such as self-timed circuits (which use hand-shaking rather than a global clock to synchronize) and globally synchronous and locally asynchronous designs. The advantage of self-timed circuits is that the switching activity is minimized in the absence of data. With a globally synchronous clock and locally asynchronous logic circuits, the loading on the clock can be greatly reduced and, thus, the clock can be run at a higher frequency. In addition, locally asynchronous logic circuits can be disabled when there is no operation. This effort will greatly reduce the power dissipation.