FPGA

Ni dung
C bn v FPGA Cu trc FPGA
CLB (Configurable Logic Block) Cc khi I/O Ma trn chuyn mch

FPGA ca Xilinx Board pht trin h thng

Nhng u im ca FPGA
FPGA l mt trong nhng thnh phn mch logic ph bin nht v cch mng ha phng php thit k cc h thng s. Mt s u im ca FPGA bao gm:
Chi ph pht trin thp Thc hin nhanh quay vng nguyn mu c h tr bi cc cng c CAD/EDA Mt tch hp cao Tc cao Lp trnh c v linh hot Mm do C th s dng li c S lng cng logic ln, cc thnh ghi, RAM v cc ngun ti nguyn nh tuyn Nhanh chng tip cn th trng SRAM FPGA cung cp nhng li ch ca CMOS truyn thng

FPGA
C hai kin trc FPGA c bn: fine-grained (ht mn) coarse-grained (ht th) S khc nhau gia cc cu trc l da vo cng ngh c dng sn xut thit b. Cc cng ngh ph bin l: Cng ngh da trn PROM/EPROM/EEPROM/FLASH Cng ngh Anti-fuse Cng ngh da trn SRAM

Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM
Control Pass Gate SRAM Cell SRAM Cell

Multiplexer 0 or 1 MUX

Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM
Nhc im Bay hi Yu cu b nh vnh vin bn trong Yu cu din tch ln

u im Lp trnh li c, d dng v nhanh chng Ch yu cu mch tch hp chun cho cng ngh lp trnh (tri ngc vi Antifuse)
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Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM

Cng ngh AntiFuse

Lm ln ln mt antifuse
Amorphous silicon column Metal Oxide Metal Substrate Polysilicon via

(a) Before programming

(b) After programming

Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM
Nhc im Khng lp trnh li c; cc lin kt c lm vnh vin Yu cu mch ph tr pht in p lp trnh cao

u im Kch thc nh Tr khng ni tip kh nh in dung k sinh thp

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Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM
Word Line Bit Line

--

Control Gate Oxide Layer Floating Gate

Drain Word Line Bit Line

Source

-------

Control Gate Oxide Layer Floating Gate

Drain

Source
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Cng ngh lp trnh chuyn mch

SRAM Antifuse EPROM
Nhc im Tr khng cao ca transistor EPROM Tiu th cng sut tnh cao Chiu nh sng tia cc tm cn phi lp trnh li

u im Khng yu cu b nh ngoi; b nh vn duy tr khi mt ngun

C th lp trnh li c
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Cng ngh lp trnh chuyn mch

Bng tm tt cng ngh lp trnh
Technology Fusible-link Antifuse EPROM E2PROM/ FLASH SRAM
SRAM

Symbol

Predominantly associated with ... SPLDs FPGAs SPLDs and CPLDs SPLDs and CPLDs (some FPGAs) FPGAs (some CPLDs)

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Cu trc FPGA
Cu trc ht mn (Fine-grained)
Cu trc ht mn c lp rp t nhiu cng logic hoc transistor hoc macrocells nh Vi lp trnh c lin kt ni (interconnect) gia chng

Hu nh tri ngc vi CPLD

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Cu trc FPGA
Cu trc ht th (Coarse-grained)
Cu trc ht th FPGAs bao gm cc macrocell ln hn Thng thng, cc macrocell bao gm cc Flip-Flop v cc bng Look Up (LUT), chng c dng thc hin cc hm logic t hp Trong a s cc cu trc, bng look-up 4 ng vo (xem nh l ROM 16x1) thc hin logic thc t Khi logic ln hn thng ci thin s thc hin khi so snh vi cu trc ht mn (fine-grained)

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Cng ngh lp trnh FPGA

Cng ngh PROM/EPROM/EEPROM/FLASH
Qu trnh lp trnh c thc hin bn ngoi mch v c th hoc khng th lp trnh li c
PROM l thit b lp trnh mt ln (OTP) ch c th lp trnh c mt ln

Cc cell EPROM c lp trnh bng in bng mt thit b lp trnh thit b Mt vi thit b da trn EPROM c th xa c bng tia cc tm nu c chiu vo ca s trn v EEPROMs c sn xut vi v nha gi thp
Cc v nha khng th xa c bng tia cc tm, chng c xa bng in

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Cng ngh lp trnh FPGA

Cng ngh PROM/EPROM/EEPROM/FLASH
Mt nh Electrically-Erasable-ProgrammableRead-Only-Memory (EEPROM) c cu trc vt l ln hn nhiu mt nh EPROM nhng c u im l xa c bng in m khng yu cu xa bng tia cc tm.
Thit b EEPROM c th xa c, thm ch trong mt v nha gi thp.

FLASH-xa c (hoc xa nhiu) electrically erasable programmable read-only memory.

FLASH c th xa c bng in nh EEPROM nhng kch thc nh nh, kinh t hn cng ngh EPROM.

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Cng ngh lp trnh FPGA

Cng ngh Anti-fuse
Anti-fuse l lp trnh c mt ln (OTP) Cc cu ch c t mt cch vnh vin Phn anti ca anti-fuse c c bng cch lp trnh
Thay cho vic lm gy mt lin kt kim loi bng cch cho dng in i qua n, mt lin kt c ln ln lm kt ni

Anti-fuses hoc l silicon v nh hnh hoc kt ni kim loi vi kim loi

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Cng ngh lp trnh FPGA

Cng ngh Anti-fuse
Nhng u im ca anti-fuse FPGA bao gm:
Chng c kch thc vt l kh nh Chng c tr khng kt ni thp

Nhng nhc im bao gm:

Chng yu cu mt lng ln transistor lp trnh trn thit b Chng khng th s dng li c (chng l loi OTP)

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Cng ngh lp trnh FPGA

Cng ngh SRAM
Cc cell SRAM c thc hin nh cc b to hm m phng logic t hp v cng c dng iu khin cc b a hp v cc ngun ti nguyn nh tuyn y l cng ngh ph bin nht hin nay Phng php ny tng t cng ngh c dng trong cc thit b RAM tnh nhng vi mt vi sa i
Cc cell RAM trong mt thit b nh c thit k c th thc hin c/ghi nhanh nht Cc cell RAM trong mt thit b lp trnh c thng c thit k n nh thay cho hiu sut c/ghi Do , cc cell RAM trong mt thit b lp tnh c c 1 tr khng thp kt ni vi Vcc v GND cung cp n nh cao nht trn cc dao ng in p
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Cng ngh lp trnh FPGA

Cng ngh SRAM
Bi v b nh tnh l bay hi (ni dung s bin mt khi tt ngun), thit b da vo SRAM c khi ng" sau khi m ngun iu ny lm cho chng c th lp trnh trn h thng hoc c th lp trnh li, thm ch trong thi gian thc Kt qu l, FPGA da trn SRAM thng cu hnh li trong cc ng dng my tnh ni m chc nng ca thit b c thay i mt cch t ng

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Cng ngh lp trnh FPGA

Cng ngh SRAM
Qu trnh cu hnh thng ch yu cu ti a mt vi trm ms Hu ht cc thit b da vo SRAM c th t khi ng mt cch t ng khi cp ngun ging nh nhiu b vi x l Hu ht cc thit b da vo SRAM c thit k lm vic vi hoc PROM byte-rng chun hoc vi PROM truy xut tun t ni tip

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FPGA
Trong lch s, cu trc FPGA v cc cng ty bt u khong thi gian tng t nh CPLD FPGA gn vi ASIC lp trnh c
Nhn mnh nhiu vo nh tuyn kt ni Thi gian l kh d on -- multiple hops so vi thi gian tr c nh ca mt ma trn chuyn mch CPLD Nhng kh nng m rng nhiu hn t kch thc ln

FPGA c cc khi logic lp trnh c ch c mt vo ng vo v 1 hoc 2 flip-flop, nhng nhiu hn nhiu so vi s lng macrocell c trong mt CPLD
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FPGA
Cu trc tng qut chip FPGA, coarse-grained

CLB: khi logic cu hnh c

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FPGA
FPGAs khng cha mng AND hoc OR Ba thnh phn chnh:
Cc khi logic Cc khi I/O Dy ni lin kt ln nhau v cc chuyn mch
Tt c cc thnh phn u c th lp trnh c
I/O Block 24 Interconnection Switches Logic Block

Cc khi khc ca FPGA

Phn b xung clock Cc khi b nh nhng Cc khi chc nng c bit:
Khi DSP:
Phn cng b nhn, b cng v thanh ghi

B vi x l/vi iu khin nhng B thu pht ni tip tc cao

FPGA Phn t logic c bn

LUT thc hin logic t hp Thanh ghi cho mch tun t Logic cng (khng cho thy):
Thc hin logic cc hm s hc M rng logic cho cc hm yu cu nhiu hn 4 ng vo
Select

Out A B C D

LUT
Clock

Bng Look-Up (LUT)

Bng Look-up (Look-up table) vi N-ng vo c th c dng thc hin bt k hm logic no c N ng vo LUT c lp trnh vi bng s tht
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0

A B C D

LUT
Thc hin LUT

A B Z C D

Bng s tht

Thc hin Cng

Thc hin LUT

V d: LUT 3 ng vo X1 Da vo cc b a hp X2 (pass transistors) Cc mc ca LUT c lu tr trong cc nh cu hnh

0/1
0/1

0/1 0/1
0/1 0/1 0/1 0/1 F

cc nh cu hnh

X3

Cc khi khc ca FPGA

Phn b xung clock Cc khi b nh nhng Cc khi chc nng c bit:
Khi DSP:
Phn cng b nhn, b cng v thanh ghi

Cc b vi x l/vi iu khin nhng B thu pht ni tip tc cao

Tnh nng c bit

Qun l xung clock
PLL,DLL (Delay Lock Loop) Loi tr lch xung gia xung clock bn trong v xung clock trn chip Low-skew mng phn b xung clock ton cc

H tr cho nhiu giao din chun khc nhau Cc I/O ni tip tc cao Li vi x l nhng Khi DSP (Digital Signal Processing)

Cc thnh phn cu hnh lu tr

Static Random Access Memory (SRAM)
Cu trnh logic c iu khin bi trng thi ca cc bit SRAM FPGA cn phi c cu hnh lc m ngun bi ROM c tch ri khc

Flash Erasable Programmable ROM (Flash)

Cu hnh logic c thc hin bi cc transistor cc cng-th ni c th ngt bng cch tim chch in tch vo cc cng ca n. FPGA t n gi chng trnh Lp trnh li c, thm ch trn mch

FPGA
Xilinx cp n cc chuyn mch kt ni nh cc ma trn chuyn mch IOB IOB IOB IOB
IOB IOB

CLB
SM

CLB
SM

CLB
SM

CLB

IOB

Ma trn chuyn mch lp trnh c

IOB

CLB
SM

CLB
SM

CLB
SM

CLB

IOB

IOB

CLB
SM

CLB
SM

CLB
SM

CLB

IOB

IOB

CLB
IOB

CLB
IOB

CLB
IOB

CLB
IOB

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FPGA
Ma trn chuyn mch lp trnh c
Phn t chuyn mch lp trnh c

turning the corner, etc.

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Khi logic FPGA

Cc cell lu tr trong cc LUT trong mt FPGA l bay hi
Mt ni dung lu tr khi tt ngun

S dngPROM gi d liu vnh vin Cc cell lu tr c ti mt cch t ng t PROM khi chip c bt u

Select

Logic Block

x1 Out
LUT

In1 In2 In3 In4

LUT
Clock

D Q

0/1 0/1 0/1 0/1

x2

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FPGA
Mt v d lp trnh mt FPGA
x3 f

f1 x1 x2
x1
x1 x2 0 0 0 1 x2 0 1 0 0

f 2 x2 x3
f2

f1
x3

f x1 x2 x2 x3

x2

f1 f2

0 1 1 1

f3

x1 LUT 0/1 0/1 0/1 0/1 f

x2

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FPGAs
Mt v d lp trnh mt FPGA
x3 f

f1 x1 x2
x1
x1 x2 0 0 0 1 x2 0 1 0 0

f 2 x2 x3
f2

f1
x3

f x1 x2 x2 x3

x2

f1 f2

0 1 1 1

f3

x1 LUT 0/1 0/1 0/1 0/1 f

x2

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Xilinx 4000-Series FPGAs

c tnh ca FPGA Xilinx 4000-series

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Khi logic cu hnh c (CLB)

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B to hm logic
Bng Look-Up (LUT)
B nh lu tr cc bng truy vn

F, G
16 x 1 SRAM

H
8 x 1 SRAM

Khng th cu hnh nh b nh

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B to hm CLB (F, G, H)
Dng RAM lu tr bng s tht
F, G: 4 ng vo, 16 bit ca mi RAM H: 3 ng vo, 8 bit ca RAM RAM c ti t mt PROM bn trong lc h thng bt u.

Kh nng s dng F, G, v H rng:

Bt k 2 chc nng ca 4 bin, cng vi mt chc nng 3 bin Bt k chc nng ca 5 bin Bt k chc nng ca 4 bin, cng vi mt vi chc nng ca 6 bin Mt vi chc nng ca 9 bin, bao gm chn l v 4-bit cascadable equality checking

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FPGA
Cc kt ni ng vo v ng ra CLB b chn vi trong bin kt ni

CLB

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Chi tit

CLB
Cc kt ni c iu khin bi cc bit RAM
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Cng vic ca Fitter

Phn chia cc hm logic thnh CLBs Sp xp CLB Kt ni CLB Ti thiu s lng CLB c dng Ti thiu kch thc v thi gian tr ca kt ni c s dng Lm vic vi cc rng buc
Kha cc chn I/O Critical-path delays Thi gian setup v gi ca cc phn t lu tr
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Khi I/O

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Spartan-II FPGA

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Kt cu Logic
Logic Cell
Bng Lookup (LUT) Flip-Flop Carry logic Cc b a hp(khng cho thy)
I3 I2 I1 I0 O
SET
0 1

CE D RST Q

I3 I2 O
0 1

Lt (Slice)
Hai Logic Cells

SET CE D Q

I1
I0

RST

Spartan-3E FPGAs
2K n 33K logic cells

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B nh
Khi RAM
RAM hoc ROM Cng kp thc
Tch ri cng c va ghi
DIA DIPA DOA DOPA

ADDRA CLKA

Khng ph thuc kch thc cng

Truyn di d liu

DIB DIPB ADDRB CLKB

DOB DOPB

Xut sc cho FIFO

Block RAM Configurations Configuration Depth Data bits Parity bits 16K x 1 16Kb 1 0 8K x 2 8Kb 2 0 4K x 4 4Kb 4 0 2K x 9 2Kb 8 1 1K x 18 1Kb 16 2 512 x 36 512 32 4

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B nhn
B nhn 18 x 18
C du hoc khng du Ty chn tng pipeline Ghp tng c
18 bit 36 bit

18 bit

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Qun l xung Clock

B qun l xung clock s: Digital Clock Managers (DCM)
Clock de-skew Dch pha Nhn xung Clock Chia xung Clock Tng hp tn s
CLKIN CLK0 CLK90 CLKFX

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CLB Logic Cells (x4)

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Thit k FPGA (1)

Specification
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds..

VHDL description (Your VHDL Source Files)

Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core;

Functional simulation

Synthesis

Post-synthesis simulation

ECE 545

Thit k FPGA (2)

Implementation (Mapping, Placing & Routing)

Timing simulation

Configuration On chip testing

ECE 545

Dual-Port Block Ram (SRAM)

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Cc thnh phn Board BASYS

Mt cng c o to

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Cc thnh phn Board BASYS

100K FPGA USB2 Port Flash ROM I/O Devices PS/2 and VGA Clock Expansion Connectors

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Hng dn la chn FPGA

Xilinx Spartan-3 series FPGAs

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Tm tt
Complex Programmable Logic Devices
Cc khi chc nng
Cc mng AND v cc Macrocell

Lin kt ni lp trnh c I/O

Field Programmable Gate Arrays

Cc khi logic cu hnh c (CLB)
Cc bng Look-up

Lin kt ni lp trnh c I/O

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