Unit 2 16 Bit microprocessors 8086/8088

L1 Pin Diagram

8086
8086 is a 16-bit microprocessor fabricated using HMOS technology. 8086 has 16-bit ALU; this means 16-bit numbers are directly processed by 8086.It is a 40 pin IC. It operates at 5Mhz.Its enhanced version 8086-2 permits clock frequency 8MHz, and 8086-1, can handle upto 10MHz It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16 bits or 8 bits at a time. It has 20 address lines, so it can address up to 2 20 i.e. 1048576 = 1Mbytes of memory . Due to the 1Mbytes memory size multiprogramming is made feasible and several multiprogramming features have been incorporated in 8086 design. 8086 includes few features, which enhance multiprocessing capability (it can be used with math coprocessors like 8087, I/O processor 8089 etc. Higher Throughput (Speed)(This is achieved by a concept called pipelining).

8086 Pin Diagram

8088

8086 Pin Diagram

8086/8088 As seen in the pin diagram the two processors have the same control pin definitions except for the pins 28 and 34.Pin 28 differs only in the minimum mode. Both can operate in two modes of operation: Minimum Mode & Maximum Mode. Pin 33(MN/MX) determines the mode/configuration option. When it is connected to +5V 8086 is to be operated in minimum mode and when it is connected to ground processor will operate in maximum mode configuration. The minimum mode is used for a small system with a single processor, a system in which the 8086/8088 generates all necessary bus control signals directly. The Maximum mode is for medium size to large systems, which often include two or more processors.

8086 Pin Diagram

GND Pins 1 & 20 are grounded. Address and Data Bus Both processors multiplex the address and data signals and both have 20 address pins with address and status signals being multiplexed on the 4 most significant address pins. However because 8088 can only transfer 8 bits of data at a time, only 8 of its pins are used for data, as opposed to 16 for the 8086.The multiplexing of addresses and data or address and status reduces the number of pins needed. Pins 2 through 16 and 39 (AD0-AD15) hold the address needed for transfer during first part of the bus cycle, and are free to transfer the data during the remaining part of the cycle. INTR (Interrupt Request): is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. It can be internally masked by software resetting the interrupt enable bit.

 NMI is an edge triggered nonmaskable interrupt. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. CLK is for supplying the clock signal that synchronizes the activity within the CPU. READY is for inputting an acknowledge from a memory or I/O interface that input data will be put on the data bus or output data will be accepted from the data bus within the next clock cycle. RESET is for inputting a system reset signal. Most systems include a line that goes to all system components and a pulse is automatically sent over this line when the system is turned on ,or the reset pulse can be manually generated by a switch that allows the operator to reinitialize the system.

8086 Pin Diagram

8086 Pin Diagram

RESET (cntd) For the processor this state is having the PSW, IP, DS, SS, ES, and instruction queue cleared and CS set to FFFF. With (IP) =0000 and (CS)=FFFF the processor will begin executing at FFFF0, this location would be a read-only section of memory and would contain a JMP instruction to a program for initializing the system and loading the application software or operating system. Such a program is referred to as a bootstrap loader. Test This signal is used in conjunction with the WAIT instruction and is employed primarily in multiprocessing situations. This input is examined by the ``wait for test'' instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an``idle'' state. RD indicates that an input operation is to be performed. BHE/S7 If 0 during first part of bus cycle this pin indicates that at least one byte of the current transfer is to be made on pins AD15-AD8;if 1 transfer is made on AD7-AD0.Status S7 is output during the latter part of bus cycle, but S7 presently has not been assigned a meaning.

 ADDRESS/STATUS(AD19/S6-AD16/S3): During the first part of a bus cycle pins 35-38 output the 4 higher-order bits of the address, and during the remaining part of the cycle they output status information. Status bits S3 and S4 indicate the segment register that is being used to generate the address and bit S5 reflects the contents of the IF flag.S6 is always held at 0 indicating that an 8086/8088 is controlling the system bus. Vcc +5v Pin definitions fot the Minimum Mode. Pins 24 to 31 are mode dependent. In minimum mode these are defined as under: INTA Indicates recognition of an Interrupt request. Consists of two negative going pulses in two consecutive bus cycles. ALE Outputs a pulse at the beginning of the bus cycle and is to indicate an address is available on the address pins. DEN Output during the latter portion of the bus cycle and is to inform the transceivers that the CPU is ready to send or receive data.

8086 Pin Diagram

8086 Pin diagram

DT/R Indicates to the set of transceivers whether they are to transmit (1) or receive(0) data. M/IO Distinguishes memory transfer from an I/O transfer. It is 1 for memory transfer in 8086.In 8088 it is opposite. WR When 0,it indicates a write operation is being performed. HLDA Outputs a bus grant to a requesting master. HOLD Receives bus requests from bus masters. The 8086 will not gain control of the bus until this signal is dropped. SS0 (8088) is logically equivalent to S0 in the maximum mode Pin definitions for the Maximum Mode QS1,QS0 Reflects the status of the instruction queue. This status indicates the activity in the queue during the previous clock cycle.

8086 Pin diagram

QS1 QS0 Characteristics 0(LOW) 0 No Operation 0 1 First Byte of Opcode from Queue 1(HIGH) 0 Empty the Queue 1 1 Subsequent Byte from Queue S0,S1,S2 Indicates the type of transfer to take place during the current bus cycle: S2 S1 S0 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 write I/O port 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read memory 1 1 0 write memory 1 1 1 Inactive-passive

8086 Pin diagram

LOCK Indicates the bus is not to be relinquished to other potential bus masters. It is initiated by LOCK instruction prefix. RQ/GT1 For inputting bus requests and outputting bus grants. RQ/GT0 Same as RQ /GT1 except that a request on RQ/GT0 has higher priority.

L2 8086 Architecture

8086 Architecture

8086 Architecture
The 8086 CPU is organized as two separate units, called the Bus Interface Unit (BIU) and the Execution Unit (EU). Bus interface Unit The BIU facilitates communication between the EU and the memory or I/O circuits. It is responsible for transmitting address, data, and the control signals on the buses. It contains CS, DS, ES, SS and IP registers that hold the address of the memory locations. The IP contains the address of the next instruction to be executed by the EU. An internal bus connects the EU and BIU, and they work together. While the EU is executing an instruction the BIU fetches up to six bytes of next instruction and places it in the Instruction Queue to speed up the processor. Execution Unit The purpose of the execution unit is to execute the instruction. It contains a circuit called arithmetic and logic unit (ALU). The ALU can perform arithmetic and logical operations. The data for the arithmetic and logic operations are stored in circuits called registers.

8086 Architecture
Execution Unit(cntd) The EU has eight registers for storing data. They are AX, BX, CX, DX, SI, DI, BP and SP. In addition EU has temporary registers for holding operands for CPU, and the FLAG register whose individual bit reflect the result of a computation. Responsible for decoding and executing instruction. EU accesses the instruction from output end of the instruction queue and data from general-purpose register. During execution, EU may test the status and control flags and update these flags based on the results of execution.

8086 Architecture Registers

Registers All of the registers are 16 bits wide. According to their functions registers are divided into three groups. Data Group Which is essentially the set of arithmetic registers; Pointer Group Which includes base and index registers, Instruction pointer and Stack Pointer; Segment Group A set of special purpose base registers. Data Group consists of the AX, BX, CX, and DX registers. These registers can be used to store both operands and results and each of them can be accessed as a whole, or the upper and lower bytes can be accessed separately. For example either the two bytes in AX can be used together, or the upper byte AH or the lower byte AL can be used by itself by specifying AH or AL, respectively. In addition to serving as arithmetic registers, the BX,CX, and DX registers play special addressing, counting, and I/O roles:

8086 Architecture Registers

Data Group(cntd) BX may be used as a base register in address calculations. CX is used as an implied counter by certain instructions. DX is used to hold the I/O address during certain I/O operations. Pointer and Index group Consists of the IP, SP, BP, SI and DI registers. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers, but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segment(CS)and stack segment(SS) registers. BP is a base register for accessing the stack and may be used with other registers and/or displacement that is a part of the instruction. SI and DI registers are for indexing. Although they may be used by themselves, they are often used with the BX or BP registers and/or displacement.

8086 Architecture Registers

Segment Registers(CONCEPT Of PHYSICAL ADDRESS) Data address may be formed by adding together a combination of BX or BP register contents, SI or DI register contents, and/or a displacement*The word displacement is used to indicate a quantity that is added to the contents of a register(s) to form an EA.]. The result of such an address computation is called an Effective address(EA) or offset. The final data address, however, is determined by EA and the appropriate Data segment, Extra segment or Stack segment registers. Segment group consists of ES,SS,DS,CS registers. The registers that used for addressing, the BX, IP, SP, BP, SI, and DI registers, are only 16bits wide and, therefore an effective address has only 16bits.On the other hand, the address put on the address bus, called the physical address, must contain 20 bits. The extra 4bits are obtained by adding the effective address to the contents of one of the segment registers.

8086 Architecture Registers

Segment Registers(CONCEPT Of PHYSICAL ADDRESS) cntd The addition is carried out by appending four 0 bits to the right of the number in the segment register before the addition is made. For example if (CS)=123A and (IP)=341B,then the next instruction will be fetched from 341B Effective address 123A0 Beginning segment address -----------157BB Physical address of instruction The utilization of the segment registers essentially divides the memory space into overlapping segments, with each segment being 64k bytes long and beginning at an address that is divisible by 16. The contents of a segment register are referred to as segment address, and the segment address multiplied by 1610 as the beginning physical segment address.

8086 Architecture Registers

Address within segment
Memory 00000 123A0 Effective address (341B) 157BB Next Instruction

2239F 223A0

. . . .

8086 Architecture Registers

Advantages of using segment registers Allow the memory capacity to be 1Mbyte even though the addresses associated with the individual instructions are only 16 bits wide. Facilitate the use of separate memory areas for the program, its data and the stack. Allow the instruction ,data, or stack portion of a program to be more than 64k bytes long by using more than one code, data, or stack segment. Permit a program and/or its data to be put into different areas of memory each time the program is executed.

8086 Architecture Registers

Overlapping Segments
Memory 00000 00010 00020

first segment second segment

10000 third segment

10010
10020
. . .

8086 segmentation of memory

Advantages of segment registers In simpler and conventional approach both the code and the data reside in one contiguous area in memory and stack in some other fixed area. This is satisfactory if there is only one program in memory at a time. But in a multiprogramming environment there may be several programs in memory simultaneously. For multiprogramming it is better to keep the contiguous chunks of memory as small as possible and, therefore, it is better to separate the code from the data . Analogously, the space in ,a pail is more fully utilized by filling it with small stones than with large stones. Advantage 4 is also related to multiprogramming. For example , consider a time-sharing system in which several users are executing different programs .If there is not enough memory space, these programs are shuttled back and forth between the memory and mass

8086 segmentation of memory

Program Relocation using the CS register Memory 02000 600 Branch address =02600
. . .

Current(CS)=0200 Current code segment

1A300 600 1A900

. . .

New (CS)=1A30 Relocated code segment

8086 segmentation of memory

Advantages of segment registers (cntd) Storage. As they take turns using memory they are dynamically put into different places in memory. A given program may begin at physical address 02000 while it is currently executing. but the next time it is brought to memory it may begin at 1A300. If the program contains a branch instruction that is causing a branch to 02600,the branch will be correctly taken to 1A900 when the program is relocated to 1A300 provided that the contents of CS are changed to 1A30. Although the segments are 64k bytes long ,they can be overlapped to better utilize the memory. If a program fills only part of a segment , another segment(code, data or stack) can overlap the programs segment and the beginning address of the second segment can be within 16 bytes of the end of the program. The only wasted space would be the few bytes between the end of the program and the next 16 byte boundary.

8086 Segmentation of Memory

Overlapping Segments
Memory

Program
first 16byte boundary after the end of the program code segment Another segment

. .

8086 Architecture PSW(Flag Register)

X

0F

DF

IF

TF

SF

ZF

AF

PF

CF

8085 Flags The 8086s PSW contains 16 bits ,but 7 of them are not used. Each bit in The PSW is called a flag. The 8086 flags are divided into : conditional flags which reflect the result of the previous operation involving the ALU, and the Control flags which control the execution of special functions. Conditionl flags : SF(Sign Flag)- Is equal to the MSB of the result. Since in 2s complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0,this flag indicates whether the previous result was negative or nonnegative. ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero.

8086 Architecture PSW(Flag Register)

X

0F

DF

IF

TF

SF

ZF

AF

PF

CF

8085 Flags PF(Parity Flag)- Is set to 1 if the low order 8 bits of the result contain an even number of 1s; otherwise it is cleared. CF(Carry Flag)- An addition causes this flag to be set if there is a carry out of the MSB, and a subtraction causes it to be set if a borrow is needed. AF(Auxiliary Carry Flag)- Is set if there is carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction. This flag is used Exclusively for BCD arithmetic. OF(Overflow Flag)- Is set if an overflow occurs,i.e., a result is out of Range. For addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa.

8086 Architecture PSW(Flag Register)

X

0F

DF

IF

TF

SF

ZF

AF

PF

CF

8085 Flags OF(Overflow Flag)cntd- For subtraction it is set when the MSB needs a borrow and there is no borrow from the MSB, or vice versa. As an Example, if the previous instruction performed the addition, 0010 0011 0100 0101 + 0010 0010 0001 1001 ---------------------------------0100 0101 0101 1110 Result SF=0,ZF=0,PF=0,CF=0,AF=0,OF=0 If the previous instruction performed the addition, 0101 0100 0011 1001 + 0100 0101 0110 1010 --------------------------------1001 1001 1010 0011 Result SF=1,ZF=0,PF=1,CF=0,AF=1,OF=1

8086 Architecture PSW(Flag Register)

X

0F

DF

IF

TF

SF

ZF

AF

PF

CF

8085 Flags ControlFlags: DF (Direction Flag)-Used by string manipulation instructions .If clear, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address. IF(Interrupt Enable Flag)-If set ,a certain type of interrupt(a maskable interrupt) can be recognized by the CPU; otherwise, these interrupts are ignored. TF(Trap Flag)- If set, a trap is executed after each instruction.

8086 Architecture Internal operations(Instruction Queue) The general operation of a computer consists of: 1.Fetching the next instruction from the address indicated by the PC. 2.Putting it in the instruction register and decoding it while the PC is incremented to point to the next instruction. 3.Executing the instruction and ,if a branch is to be taken, resetting the Pc to the branch address. 4.Repeating steps 1 through 3. In 8086 the address of the next instruction is determined by the sum of IP and (CS)X16 10 ,and the instruction register is a 6 byte first in / first Out (FIFO) queue (This queue gives 8086 a pipelined architecture) that is continually being filled whenever the system bus is not needed for other operation. This look ahead feature can significantly increase the CPUs throughput because much of the time the next instruction is already in the CPU when the present instruction completes its execution.

8086 Architecture (Instruction Queue)

If a branch is to be taken, then instruction queue will have to be cleared and there is no time saving, but on average this occures only a small percentage of time. 8086 can address a word which begins with either an odd address or an even address. For the odd address case two memory references are required. One memory access is needed for the low order byte and one for the high order byte. This means that the time is saved if words are accessed at even addresses.

L3 8086 Addressing Modes

The way in which an operand is specified is called its addressing mode. The addressing modes for the 8086 instructions are broken into two Categories ,those for data and those for branch addresses. Data Related addressing modes: Immediate-The datum is either 8 bits or 16 bits long and is part of the Instruction. Direct-The 16-bit effective address of the datum is part of the instruction. Register-The datum is in the register that is specified by the instruction. For a 16 bit operand ,a register may be AX, BX, CX, DX, SI, DI, SP, or BP, and for an 8-bit operand a register may be AL,AH,BL,BH,CL,CH,DL, or DH. Register Indirect- The effective address of the datum is in the base register BX or an index register that is specified by the instruction, i.e., (BX) EA= (DI) (SI)

Addressing Modes

Register Relative- The effective address is the sum of an 8- or 16-bit Displacement and the contents of a base register or an index register,i.e., (BX) EA= (BP) 8 bit displacement (DI) + (sign extended) (SI) 16-bit displacement Based Indexed-The effective address is the sum of a base register and an index register, both of which are specified by the instruction, i.e., (BX) + (SI) (BP) (DI) Relative Based Indexed- The effective address is the sum of an 8-or 16-bit Displacement and a based indexed address, i.e., EA=

Addressing Modes

Relative Based IndexedEA= (BX) (BP)

Addressing Modes
+ (SI) + 8 bit displacement (DI) (sign extended) 16-bit displacement

For example, if (BX)=0158 (DI)=10A5 Displacement=1B57 (DS)=2100 and DS is used as the segment register, then the effective and physical addresses produced by these quantities and the various addressing modes be. Direct: EA= 1B57,Physical address=1B57+21000=22B57 Register: No effective address-datum is in specified register. Register indirect assuming register BX: EA=0158,physical address 0158+21000=21158 Register relative assuming register BX: EA=0158+1B57=1CAF,physical address=1CAF+21000=22CAF Based indexed assuming registers BX and DI:EA=0158+10A5=11FD.

Addressing Modes
Physical address=11FD+21000=221FD Relative based indexed assuming BX and DI:EA=0158+10A5+1B57=2D54, Physical address =2D54+21000=23D54 Branch Related addressing modes: Intrasegment Direct-The effective branch address is the sum of an 8 or 16 bit displacement and the current contents of IP. When the displacement is 8 bits long, it is referred to as short jump. It may be used with either conditional or unconditional branching, but a conditional branch instruction can have only an 8 bit displacement. Intrasegment Indirect-The effective branch address is the contents of a register or memory location that is accessed using any of the data related addressing modes except the immediate mode. The contents of IP are Replaced by the effective branch address. This addressing mode may be used only in unconditional branch instructions.

Intersegment Direct-Replaces the contents of IP with part of the Instruction and contents of CS with another part of the instruction. The Purpose of this addressing mode is to provide a means of branching from one code segment to another . Intersegment Indirect Replaces the contents of IP and CS with the contents of two consecutive words in memory that are referenced using any of the above data related addressing modes except the immediate and register modes. Suppose that (BX)=1256,(SI)=528F, Displacement =20A1 Then: With the direct addressing, the effective branch address is the contents Of: 20A1+(DS)X1610 With register relative addressing assuming register BX, the effective branch address is the contents of : 1256+20A1+(DS)X1610

Addressing Modes

With based indexed addressing assuming registers BX and SI, the effective Branch address is the contents of: 1256+528F+(DS)X1610

Addressing Modes

L4

Difference between 8086 & 8088

8086 is fully software compatible with 8088.The 8088 does retain the segment registers,20 bit addressing, and the features of 8086 that support multiprocessing. The ability to manipulate 16-bit operands is also preserved. The few internal differences are: The BIU in 8088 has 8-bit data bus & 16- bit data bus in 8086. Instruction queue is 4 byte long in 8088and 6 byte in 8086 8088 address pins A15 through A8 are used only for addresses and one of the control pins BHE(which is high byte enable pin),has been changed to a status pin because 8088 can access only one byte at a time. In 8086 pin 28 is IO/M ,in 8088pin 28 is IO/M

8086Bus Cycle
BUS CYCLE AND TIME STATES A bus cycle defines the sequence of events when the MPU communicates with an external device, which starts with an address being output on the system bus followed by a read or write data transfer. Types of bus cycles: Memory Read Bus Cycle Memory Write Bus Cycle Input/Output Read Bus Cycle Input/Output Write Bus Cycle The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four time states are called T1, T2, T3 and T4.

8086Bus Cycle
MEMORY READ CYCLES Fig. (a) shows a memory read cycle of the 8086: During period T1, The 8086 outputs the 20-bit address of the memory location to be accessed on its multiplexed address/data bus. BHE is also output along with the address during T1. At the same time a pulse is also produced at ALE. The trailing edge or the high level of this pulse is used to latch the address in external circuitry. Signal M/IO is set to logic 1 and signal DT/R is set to the 0 logic level and both are maintained throughout all four periods of the bus cycle. Beginning with period T2, Status bits S3 through S6 are output on the upper four address bus lines. This status information is maintained through periods T3 and T4.

8086Memory Read Cycle

On the other hand, address/data bus lines AD0 through AD7 are put in the high-Z state during T2. Late in period T2, RD is switched to logic 0. This indicates to the memory subsystem that a read cycle is in progress. DEN is switched to logic 0 to enable external circuitry to allow the data to move from memory onto the microprocessor's data bus. During period T3, The memory must provide valid data during T3 and maintain it until after the processor terminates the read operation. The data read by the 8086 microprocessor can be carried over all 16 data bus lines. During T4, The 8086 switches RD to the inactive 1 logic level to terminate the read operation. DEN returns to its inactive logic level late during T4 to disable the external circuitry.

8086 Memory Read Bus Cycle

8086 Memory Write Bus Cycle

MEMORY WRITE CYCLES Fig.(b) shows a memory write cycle of the 8088: During period T1, The address along with BHE are output and latched with the ALE pulse. M/IO is set to logic 1 to indicate a memory cycle. However, this time DT/R is switched to logic 1. This signals external circuits that the 8086 is going to transmit data over the bus. Beginning with period T2, WR is switched to logic 0 telling the memory subsystem that a write operation is to follow. The 8086 puts the data on the bus late in T2 and maintains the data valid through T4. Data will be carried over all 16 data bus lines. DEN enables the external circuitry to provide a path for data from the processor to the memory.

8086 Memory Write Bus Cycle

8086 Memory Organization

For general memory organization refer to unit 1.8086 memory organization is as follows: The memory address space of the 8086-based microcomputers has different logical and physical organizations . Logically, memory is implemented as a single 1M 8 memory chunk. Physically, memory is implemented as two independent 512Kbyte banks: the low (even) bank and the high (odd) bank. Data bytes associated with an even address (00000, 00002, etc.) reside in the low bank, and those with odd addresses (00001, 00003, etc.) reside in the high bank. Address bits A1 through A19 select the storage location that is to be accessed. They are applied to both banks in parallel. A0 and bus high enable (BHE) are used as bank-select signals.

8086 Memory Organization

(a) Logical memory organization, and (b) Physical memory organization (high and low memory banks) of the 8086 microprocessor.

8086 Memory Organization

Each of the memory banks provides half of the 8086's 16-bit data bus. The lower bank transfers bytes of data over data lines D0 through D7, while data transfers for a high bank use D8 through D15. The 8086 microprocessor accesses memory as follows: Fig. (a)shows how a byte-memory operation is performed to address X, an even-addressed storage location. A0 is set to logic 0 to enable the low bank of memory and BHE to logic 1 to disable the high bank. Data are transferred to or from the lower bank over data bus lines D0 through D7. Fig.(b) shows how a byte-memory operation is performed to an odd addressed storage location such as X + 1. A0 is set to logic 1 and BHE to logic 0.This enables the high bank of memory and disables the low bank. Data are transferred over bus lines D8 through D15. D8 represents the LSB. Fig.(c) illustrates how an aligned word (at even an address X) is accessed. Both the high and low banks are accessed at the same time.

8086 Memory Organization

Both A0 and BHE are set to 0. This 16-bit word is transferred over the complete data bus D0 through D15 in just one bus cycle. Fig.(d) illustrates how a misaligned word (at address X + 1) is accessed. Two bus cycles are needed. During the first bus cycle, the byte of the word located at address X + 1 in the high bank is accessed over D8 through D15. Even though the data transfer uses data lines D8 through D15, to the processor it is the low byte of the addressed data word. In the second memory bus cycle, the even byte located at X + 2 in the low bank is accessed over bus lines D0 through D7.

8086 Memory Organization

8086 Memory Organization