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The original analog signal

filtered by an anti-aliasing filter to remove any high-frequency components The signal is sampled and hold and then converted into a digital signal

Next the DAC converts the digital signal back into an analog signal.
Note that the output of the DAC is not as "smooth" as the original signal. LPF returns the analog signal back to its original form (plus phase shift introduced from the conversions)

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

NYQUIST CRITERION
Defines how fast the sampling rate needs to be to represent an analog signal accurately. This criterion requires that the sampiing rate is at least two times the highest frequency contained in the analog signal.
In our example, we need to know how quickly the weather can change and then take samples twice as fast as that value.

The Nyquist Criterion can be described as

Fsampling 2.Fmax

How much resolution should we use to represent the analog signal accurately? There is no absolute criterion

In our weather example, if we were only interested in following general trends, then the 25 quantization levels would more than suffice. However, if an accurate record of the temperature to within 10.5" F, we would need to double the resolution to 50 quantization levels so that each quantization level would correspond to each degree +0.5" F
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Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Sample Mode

the time required for the S/H to track the analog signal within a specified tolerance is known as the acquisition time if the input changes very quickly, then the output of the T/H could be limited by the amplifier's slew rate The amp stability is extremely critical. If the amplifier is not compensated correctly, and the phase margin is too small, then a large overshoot will occur. A large overshoot requires a longer settling time for the S/H to settle within the specified tolerance.

Hold mode
pedestal error occurs as changing its voltage. Droop, the leakage of current from the capacitor due to parasitic impedance,
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Aperture error The aperture time actually varies slightly as a result of noise on the hold-control signal and the value of the input signal. Aperture uncertainty/jitter -> sampling error

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com