A

LECTURE
ON
PIPELINED ADC
INTRODUCTION :

ADC (Analog-to Digital converter):

Mixed Signal

Performs both analog and digital
functions.

Analog input
Voltage or current

ADC reference
Against which the input is compared

Digital output
Indicates the fraction of ADC reference equivalent to input signal.
A/D
Converter
V
CC
V
REF
GND
Analog
Input
Digital
Output
RESOLUTION OF ADC:

The minimum input signal value that can be resolved.
usually stated in No of bits

The size of Least significant Bit.

More no of bits indicates better resolution



0 1 0 0 1 1 . 0 1
MSB(Most Significant Bit)
LSB(Least Significant Bit)
In a digital word the MSB has a weight of 2
(N-1)
and the
LSB has a weight of 1 , where, N is the no of bits of the
digital word
Significance of LSB:

1 LSB = V
REF
/ 2
N
,

Where N is the no. of Bits of the Digital word and
V
REF
is the ADC reference.
Accurate ADC:

higher resolution ADC (higher no of bits)
- Reduced SNR (signal to noise ratio) performance of the ADC
- Small signal lost in noise
or smaller ADC Reference
- Reduced input dynamic range
- Reduced SNR performance
Errors in ADC:

Quantization error :
1LSB
1LSB
8
REF
V
8
REF
3V
8
REF
5V
8
REF
7V
Input (V)
4
REF
V
4
REF
3V
2
REF
V
REF
V
0
111

110

101

100

011

010

001

000
D
i
g
i
t
a
l

O
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t
p
u
t

0
The magnitude of error varies from 0 to 1LSB
Figure shows a quantization error of 1 LSB for 3bit ADC.



If we add an offset of LSB then the error will reduce to LSB.
Analog Input (V)
8
1
8
3
8
5
8
7
4
1
4
3
2
1
FS
0
111

110

101

100

011

010

001

000
D
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a
l

O
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p
u
t

ACTUAL
SHIFTED
ACTUAL
IDEAL
Gain Error
Full scale
Offset Error
Offset Error
Gain and Offset errors :
Analog Input (V)
111

110

101

100

011

010

001

000
D
i
g
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t
a
l

O
u
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p
u
t

8
1
8
3
8
5
8
7
4
1
4
3
2
1
FS
0
0.3 LSB
DNL=-0.7
1 LSB
DNL=0
1.2 LSB
DNL=+0.2 Actual
Ideal
Missing code
DNL (Differential Non Linearity)
Analog Input (V)
111

110

101

100

011

010

001

000
D
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g
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t
a
l

O
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t
p
u
t

8
1
8
3
8
5
8
7
4
1
4
3
2
1
FS
0
0.6 LSB maximum error
INL = 0.6 LSB
Actual straight line
ideal straight line
INL (Integral Non Linearity)
Noisy Signal Noise Signal
A
m
p
l
i
t
u
d
e

i
n

(
d
B
)

Frequency in (Hz)
Signal
Noise
Noise Performance of ADC:
Signal to Noise Ratio(SNR):

SNR (ideal ADC)=6.02n + 1.76 dB
n is the No. of Bits of ADC

Analog
Spectrum
analyzer
x 3x 5x
Square Wave
Frequency x
A/D
FFT
x 2x 3x 4x 5x
Harmonic Distortion
Pure sine Wave
Frequency x
Analog
Spectrum
analyzer
x
Pure sine Wave
Frequency x
Total Harmonic Distortion of ADCs:
Continue
2
1
2 2
3
2
2
f
fn f f
v
v v v
THD
..........
Where v
f1
is the fundamental Amplitude
V
f2
is the second harmonic amplitude etc..

Noise Performance Parameters of ADC:
Continue ..


SFDR:

Spurious Free Dynamic Range (SFDR) is the difference between the value of the desired
output signal and the value of the highest amplitude output frequency that is not present in the
input, expressed in dB.

SINAD:

Signal-to-Noise And Distortion (SINAD) is a combination of the SNR and the THD
specifications.
Continue ..
Input Dynamic Range:

Dynamic Range is the ratio of the largest to the smallest possible signals that
can be resolved.


Where n is the No. of Bits of ADC
ENOB:

ENOB says that the ADC is equivalent to this (ENOB) number of bits as far as SINAD is
concerned. That is, a converter with an ENOB of 9.0 has the same SINAD as a theoretically
perfect 9-bit converter

6.02
1.76 SINAD
ENOB

=
Fast Fourier Transformation of ADC Output:
Continue ..
spurious free dynamic range is determined by the highest spur level
Different type of ADCs:
Flash ADC:

- Performed by highly parallel comparison of analog input signal
with multiple reference Levels.

- Multiple comparison need multiple comparators

- Very high speed and accuracy

- High component count with higher power consumption

- Higher input capacitance

SAR ADC:
- Use one or a few comparators

- Operates iteratively to achieve high accuracy conversion

- Performs a binary search using a DAC and a comparator

- Operates at much slower speed
takes N cycles to complete a conversion where N is the No.
of bits
Delta sigma ADC:
- Achieves higher resolution by oversampling the input signal
and noise shaping

- Relatively slow

- Often used in mixed signal integrated A/D insensitivity to CMOS
process mismatch concern compared to other ADCS.

Continue ..
Pipelined ADC:


- Pipelined ADC behaves similarly to flash type of ADC except for a
finite amount of latency between the analog sample and the digital
representation of the sample.

- The latency depends on the no of pipelined stages.

- Slower than flash ADC but faster than others

- The component count increases linearly with the resolution unlike
the exponential increase in case of flash ADC.

- Relatively compact, inexpensive and power efficient for high speed
applications.





Continue ..
ADC Application:
17
,
Pipeline ADC dominates in the high speed application field.
Origin of Pipelined ADC:
E
N
C
O
D
E
R
Digital Output
2
n-1
Comparators
VREF VIN
1. The flash ADC:
High Speed Application

Each comparator has its own
threshold voltage, spaced by
1 LSB,

The output of the comparators
is in thermometer format,

An encoder is used to convert
to convert the thermometer
codes into binary format

Hardware count increases
exponentially
2.Sub Ranging ADC:
3 Bit ADC
DAC
3 Bit ADC
-
Sign
Gain
LSB
MSB
VIN
Continue ..
The input signal is first converted
Digital form by a simple 3-bits flash
ADC to get the MSB Bits.

the residue is obtained by subtracting
analog output of the DAC, which is fed
by MSB Digital Bits.

The residue is multiplied with a Gain
and converted in to Digital form
to get the LSB.


Stage1 Stage2
3 Bits + 3 Bits
Sub Ranging ADC:
Continue ..
-Very High Speed

-1 Conversion/Clock

-1/2 Clock Latency

- Higher Resolution with Less hardware

- Smaller Input Capacitance

- Requires High Precision interstage
Processing

- Hardware Still Increases Exponentially
within Each Flash
VIN
Architecture of a pipelined ADC:
STAGE 1 STAGE 2 STAGE N
Digital Delay Logic
Digital out
MDAC
(x2)
Sub-ADC
VRES1
DOUT
1 Bit
VRES2
Working of pipeline ADC:
VREF
0
D=1
D=0
VREF VREF
0 0
Stage2 Stage4 Stage1
( ) VIN 2
0 1 1
|
.
|

\
|

2
VREF
VIN 2
0.6
0.5
0.4
0.8
0.7
VREF
Stage3
0
1
Output=11
0
VREF
VIN
VRES
D=1 D=0
VREF 0
V
IN
-
+
A
-

+
VRES
C1
C2
- +
2
+V
REF
2
2
1
1
S1
S2
S3
S4
S5
0
2 is the sampling phase
1 is the amplifying phase
Multiplying DAC(MDAC)
If D=1 |
.
|

\
|
=
2
VREF
VIN 2 VRES
If D=0
VIN 2 VRES=
Errors In Pipelined ADC:
D=1 D=0
0
VIN
VREF
VRES
0 VREF
VIN
VRES
Ideal Residue plot
Residue plot
With Charge Injection
Cause of Missing Decision level Cause of Missing Decision level
Cause of Missing Decision level
Cause of Missing Decision level
0
0
VREF
VREF
VIN
VIN
VRES
VRES
Residue plot
With Comparator offset
Residue plot
With Capacitor Mismatch
Continue ..
Effect of a threshold error (comparator offset):
0.5V
(Mid)
0V
1v
0.7V
1 0 0 1
shift
Output=9
Stage2 Stage3 Stage4 Stage1
O
u
t
p
u
t

R
a
n
g
e

Input Range
VIN
Input Range
VIN
O
u
t
p
u
t

R
a
n
g
e

Saturated
input
Residue
Residue
O
u
t
p
u
t

R
a
n
g
e

Input Range
VIN
Saturated
input
Residue
Threshold
error
stage3
stage4
stage2
Continue ..

Effect of threshold error on residue of different pipelined
Stages:
Basic Block 2 BIT A/D Basic Block
D
D
D
D
D
D
D
D
D
D D D
+ + +
carry carry
2bit
D/A
2bit
A/D
Digital out

x2
VIN
-
+ Residue
D1 D3(MSB) D0(LSB) D2
1.5 Bit per Stage pipelined Architecture:
0.25V
0V
1V
0.3V
01 01 10
Output=11
Stage2 Stage3 Stage1
0.375V
0.675V
0.5V
0.675V
0.375V
0.5V
0.25V
0.5V
0.75V
0V 0V
1V 1V
0.7V
0.4V
( ) VIN 2
|
.
|

\
|

4
VREF
VIN 2
|
.
|

\
|

2
VREF
VIN 2
D=11
D=00
D=01
D=10
D=10
D=01
D=00
+ + +
Carry=0 Carry=0
1 0 1 1
Working of 1.5 Bit per Stage pipelined Architecture:
2bit
D/A
2bit
A/D
2
Digital out

x2
VIN
-
+
Residue
VREF/2
Residue
VREF
5VREF/8
Out=10 Out=00 Out=01
VIN
0
3VREF/8
(VREF/2,0)
Residue Plot of 1.5 Bit per Stage pipelined Architecture:
0.25V
0V
1V
0.3V
shift
Stage2 Stage3 Stage1
0.375V
0.675V
shift
0.5V
0.675V
0.375V
0.5V
0.25V
0.5V
0.75V
0V 0V
1V 1V
0.7V
0.4V
01 01 10
Output=11
+ + +
Carry=0 Carry=0
1 0 1 1
Tolerance of 1.5 Bit per Stage pipelined Architecture
to Threshold Error:
Designed of a 1Bit per Stage pipelined ADC
in 0.35u AMS technology:




Sampling speed : 5MS/s

Supply voltage : 3.3V

Resolution : 10 bit
Pipelined Architecture :
Clock Diagram:
Sample and Hold:
Multiplying Digital to Analog (MDAC):

Architecture of Op-Amp & sampling
Switches(S1-S4):
38
Op-Amp specifications:
Dc Gain 75 dB
Phase Margin 65
Slew Rate 8 V/sec
W
3dB
1KHz
UGB 96MHz
Output Impedance 3K
Comparator Architecture:
Static Characteristics
(Histogram Method):
Dynamic Testing:
Differential Non-linearity(DNL):
Integral Non-linearity(INL):
FFT Analysis:
Input sinusoidal freq. = 4.883 KHz , sampling rate=5MS/s,
SNR= 64 dB,SFDR=64.07dB.
SFDR = 64.07dB
44
ADC Output with Var. Freq. and Var. Ampl. Sinusoidal:
The marked section of the graph shows an offset of 5mV around
Input voltage range of 50mV
45
Layout of the complete chip: