It is based on a pair of diode connected transistor that is biased with a constant current source, and a CMOS voltage difference

circuit. Gilbert's translinear circuit is widely used for the design of multiplier circuits A new CMOS voltage-mode Four-quadrant analog Multiplier is formed by cascading the complementary diode pair connection with the voltage difference circuit.

The multiplier proposed also uses the MOS square law characteristics. The square-law based MOS multiplier can be realized easily.

An analog multiplier provides basic building blocks to design many analog signal processing systems,for example Adaptive filter,Curve fitting generators.
The output voltage of multiplier appears directly from the MOS active load transistors.

It is use to design analog signal processing system. For example filter, generator. It is also applied to amplitude modulation, frequency translation, automatic gain control, squaring, square rooting and neural networks. It is used in many electronics devices. It is also used to design multiplier circuit in bipolar and CMOS technologies.

The implementation of MOS analog multiplier making use of the features of MOS devices would be better approach. It operated on low a power voltage. It consume less time as compared to another hardware circuitary.

The dynamic range and frequency performance of a multiplier are limited.

 SOFTWARE

USED:

Tanner s-edit 13.0 version software.

A new CMOS voltage mode four quadrant multiplier based on the square-law characteristic. The multiplier achieves about 0.800 linearity error when the input voltage is 400 mV. The total harmonic distortion is less than 0.620% and the -3dB bandwidth is 30 MHz.

B.Gilbert, A precise four-quadrant multiplier with subnanosecond response, IEEE J. solid state circuits, vol. sc-3, no.4, pp. 365-373 1998. J.N.Babanezhad and G.C. Temes,A 20v four quadrant CMOS analog multiplier.IEEE J. solid state circuits, 1998, sc-20, app.1158-1168. Zhenhua Wang,A four Transistor Four Quadrant Analog Multiplier using MOS Transistor operating in the saturation region, IEEE Trans. Instrum.Meas,vol.42, no.1 pp.75-77, Feb.1993. Sho-Yuan Hsiao and Chung-Yu Wu, "A 1.2 V CMOS FourQuadrant Analog Multiplier," IEEE ISCAS'05 Proceedings, pp. 24 1244, June 1997. Boonchai Boonchu and Wanlop Surakampontorn, "A New NMOS Four-Quadrant Analog Multiplier," IEEE ISCAS '05 Proceedings, pp. 1004-1007, May 2005.

THANK YOU