Microprocessor Final Ver1 Part7

DHBK 2005
Ni dung mn hc
1. 2. 3. 4. 5. 6. 7. Gii thiu chung v h vi x l B vi x l Intel 8088/8086 Lp trnh hp ng cho 8086 T chc vo ra d liu Ngt v x l ngt Truy cp b nh trc tip DMA Cc b vi x l trn thc t
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Chng 7: Cc b vi x l trn thc t

General purpose microprocessors
Intel 80x86 Xu hng pht trin
Microcontrollers
Vi iu khin ca Motorola H vi iu khin 8051 H vi iu khin AVR PSOC Xu hng pht trin
Digital signal processors

Texas Instruments Motorola Philips Xu hng pht trin
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Microcontrollers

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Intel 4004
First microprocessor (1971) 4-bit processor 2300 Transistors (PMOS), 10 mm 0.06 MIPS, 108 KHz, 640 bytes addressable memory -15V power supply
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Intel 8008
First 8-bit processor (1972) Cost $500; at this time, a 4-bit processor costed $50 Complete system had 2 Kbyte RAM 200 KHz clock frequency, 10 mm, 3500 TOR, 0.06 MIPS, 16 Kbyte addressable memory 18 pin package, multiplexed address and data bus
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Intel 8080
Second gen. 8-bit processor, introduced in 1974 40 pin package, NMOS, 500K instructions/s, 6 mm, 2 MHz, 5V & +12V power supply, 6 KTOR, 0.64 MIPS 64 Kbyte address space (as large as designers want, EDN 1974)
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Intel 8088
16-bit processor introduced in 1979 3 mm, 5 a 8 MHz, 29 KTOR, 0.33 a 0.66 MIPS, 1 Mbyte addressable memory
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Intel 8086
16 bit integer CPU 16 data
20
address
Introduced: 1978 Clock frequency: 8 - 10 MHz
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Intel 80286
MMU 16 bit integer CPU 16 data
24
address
Introduced: 1983 1.5 mm, 134 KTOR, 0.9 to 2.6 MIPS Clock frequency: 6 - 25 MHz
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Intel 80386sx
24
address
Introduced: 1986 1 mm, 275 KTOR, 16 to 33 MHz, 5 to 11 MIPS Clock frequency: 16 - 25 MHz Software support and hardware protection for multitasking
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Intel 80386dx
32
address
Introduced: 1988 Clock frequency: 16 - 40 MHz Software support and hardware protection for multitasking
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Intel 80486dx
8 Kbyte cache MMU 32 bit integer CPU 64 bit FPU 32 data
32
address
Introduced: 1989 Clock frequency: 25 - 50 MHz Software support and hardware protection for multitasking Support for parallel processing Cache required: external memory is not fast enough
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Intel 80486sx
8 Kbyte cache MMU 32 bit integer CPU 32 data
32
address

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Introduced: 1989 0.8 mm, 1.2 MTOR, 20 to 41 MIPS Clock frequency: 25 - 50 MHz Software support and hardware protection for multitasking Support for parallel processing Cache required: external memory is not fast enough
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Intel 80486dx2
8 Kbyte cache MMU 32 bit integer CPU 64 bit FPU 32 data
32
address
Introduced: 1992 Clock frequency: internal: 50 - 66 MHz, external: 25 - 33 MHz Software support and hardware protection for multitasking Support for parallel processing Cache required: external memory is not fast enough
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Intel Pentium
8 Kbyte program cache 8 Kbyte data cache Static branch prediction unit 32 bit integer pipelined CPU 32 bit integer pipelined CPU 64 bit FPU 64 data
32
address
MMU
Introduced: 1993 (.8 mm, 3.1 MTOR) up to (.35 mm, 4.5 MTOR incl. MMX) Clock frequency: internal: 60 - 166 MHz, external: 66 MHz Support for parallel processing: cache coherence protocol Super scalar
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Intel Pentium Pro

8 Kbyte L1 program cache 8 Kbyte L1 data cache Dynamic branch prediction unit 32 bit integer pipelined CPU 32 bit integer pipelined CPU 32 bit integer pipelined CPU 64 bit pipelined FPU Address generation unit to L2 cache 64+ECC data
36
address
MMU
Instruction dispatch unit
Introduced: 1995, 0.35 mm, 3.3 V, 5.5 MTOR, 35W, 387 pin Clock frequency: 150 - 200 MHz Internal, 60 - >100 MHz External Super scalar (4 Instr./cycle), super pipelined (12 stages) Support for symmetrical multiprocessing (4 CPU) MCM: 256-1024 Kbyte L2 4-way set associative cache
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Intel Pentium II
16 Kbyte L1 program cache 16 Kbyte L1 data cache Dynamic branch prediction unit 32 bit integer pipelined CPU 32 bit integer pipelined CPU 64 bit pipelined FPU 64 bit pipelined FPU Address generation unit ECC to L2 cache 64+ECC data
36
address
MMU
Introduced: 1997, 0.25 mm, 2.0 V, 9 MTOR, 43 W, 242 pin Clock frequency: 200 - 550 MHz Internal, 100 - 225 MHz L2 cache, 66 - 100 MHz External Super scalar (4 Instr./cycle), super pipelined (12 stages) Support for symmetrical multiprocessing (8 CPU) Single Edge Contact Cartridge with Thermal Sensor: 256-1024 Kbyte L2 4-way set associative cache
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Intel Pentium III

16 Kbyte L1 program cache 16 Kbyte L1 data cache
256 Kbyte L2 unified cache
32 bit integer pipelined CPU 32 bit integer pipelined CPU 64 bit pipelined FPU 64 bit pipelined FPU Address generation unit
64+ECC data
36
address
Dynamic branch prediction unit
MMU
Introduced: 1999, 0.18 mm , 6LM, 1.8 V, 28 MTOR, 370 pin Clock frequency: 450 - 1130 MHz Internal, 100-133 MHz External Super scalar (4 Instr./cycle), super pipelined (12 stages) Support for symmetrical multiprocessing (2 CPU)
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Intel Pentium IV
16 Kbyte L1 program cache 16 Kbyte L1 data cache
256/512/1024 Kbyte L2
32 bit integer pipelined CPU 32 bit integer pipelined CPU 64 bit pipelined FPU 64 bit pipelined FPU Address generation unit
64+ECC data
36
address
Dynamic branch prediction unit
MMU
Introduced: 2002, 0.13 mm or 90nm , 1.8 V, 55 MTOR Clock frequency: 1,4 to 3.8 GHz Internal, 400 to 800 MHz External Super scalar (4 Instr./cycle), super pipelined (12 stages) Newer versions: Hyper threading, 3.8 MHz
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Intel Pentium IV
Available at 3.80F GHz, 3.60F GHz, 3.40F GHz and 3.20F GHz Supports Hyper-Threading Technology1 (HT Technology) for all frequencies with 800 MHz front side bus (FSB) Supports Intel Extended Memory 64Technology2 (Intel EM64T) Supports Execute Disable Bit capability Binary compatible with applications running on previous members of the Intel microprocessor line Intel NetBurst microarchitecture FSB frequency at 800 MHz Hyper-Pipelined Technology Advance Dynamic Execution Very deep out-of-order execution Enhanced branch prediction 775-land Package
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Intel Pentium IV
16-KB Level 1 data cache 1-MB Advanced Transfer Cache (on-die, fullspeed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) 144 Streaming SIMD Extensions 2 (SSE2) instructions 13 Streaming SIMD Extensions 3 (SSE3) instructions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities System Management mode Multiple low-power states 8-way cache associativity provides improved cache hit rate on load/store operations
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IA-64 (Itanium)
Design started in 1994; first samples on the market in 2001 64-bit address space (4x109 Gbyte; we will never need that much) 256 64-bit integer and 128 82-bit floating point registers; 64 branch target registers; 64 1-bit predicate registers 41 bit instruction word length 10-stage pipeline separate L1 data and program, 96 Kbyte L2 unified on-chip, 4 Mbyte L3 unified off-chip
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Microcontrollers

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Trends for general purpose processors
Higher clock frequencies: 4.7 -> 30 GHz Faster memory: 120 ns -> 50 ns Limited by power dissipation => decreasing power supply voltage Parallel processing Memory with processor instead of processor with memory
not proportional to clock frequency increase => use of caches and special DRAM memories (e.g. SDRAM)
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The future: general characteristics

Roadmap 2001 Roadmap 1998 Roadmap 1995 Line width (nm) Number of masks Wafer size (mm) Number of wiring levels Power supply V: desktop Max. power dissipation/chip 1995 350 18 200 4-5 3.3 80
1997
1998 250 22 200 6 1.82.5 70
1999
2001 180 2224 300 6-7 1.51.8 90
2002 2002
2004 130 24 300 7 1.11.5 130
2004 2005
2007 90 2426 300 7-8 1.01.2 160
2007 2008
2010 65 2628 300 8-9 0.70.9 170
2010 2011
45 28
2013 2014
32 2930
2016
22
9 0.6 175
10 0.5 183 0.4
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Will 22 nm be the end of the scaling race for CMOS? Some believe10 nm will be the end thereafter, semiconductor drive will be scattered (MEMS, sensors, magnetic, optic, polymer, bio, ) Depending on application domain: besides and beyond silicon
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Besides and beyond silicon (e.g. polymer electronics)
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Besides and beyond silicon: applied to future ambient intelligent environments
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Emile Aarts, HomeLab, Philips
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Besides and beyond silicon: applied to future ambient intelligent environments
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Besides and beyond silicon: applied to ambient intelligent HomeLab (2002)
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The future: high performance (mP)

Roadmap 2001 Roadmap 1998 Roadmap 1995 Number of TOR On chip local clock freq. (MHz) On chip global clock freq. (MHz) Chip size (mm2) 1995 6M
1997
1998 11M 750 375 300
1999
2001 21M 1250 1200 340
2001 2002
2004 76M 2100 1600 430
2004 2005
2007 200M 3500 2000 520
2007 2008
2010 520M 6000 2500 620
2012 2011
1.4G 10000 3000 750
2016 2014
3.6G 16903 3674 901
300 250
CTO Intel says in 2001

2005
425 MTOR 100 nm 1600 mm2 30 GHz on chip without specific measures like individual transistor powerdown: 3000 W, i.e. 3000 amps...
1.8 GTOR in 2010

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The future: high performance (mP)
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Processor performance
Performance 1M 100K 10K 1K 100 10 1 1980 1985 1990 1995 2000 2005 Time 55%/year
Exponential growth for 3 decades! This is called Moores law: number of transistors doubles every 18 months
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(Gordon Moore, founder Intel Corp.)
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Processor performance
Smaller line size
More transistors => parallelism
1983: 1 instruction per 4 clock cycles 2002: 8 instructions per clock cycle
Smaller capacitors => faster

1983: 4 MHz 2002: 2800 MHz
Speed-up: 25000
Enables new applications

UMTS with large rolled-up OLED screen enabling web downloadable services (e.g. virtual meetings)
Do we find applications that are demanding enough for next decades processors?
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The future: DRAM

Roadmap 2001 Roadmap 1998 Roadmap 1995 Number of bits per chip Chip size (mm2) 1995 64M 190
1997
1998 256M 280
2003 1999
2001 1G 400
2007 2002
2004 4G 560
2011 2005
2007 16G 790
2016 2008
2010 64G 1120
? 2011
256G 1580
? 2014
1T 2240
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Memory density
Performance 1M 100K 10K 1K 100 10 1 1980 1985 1990 1995 Memory 10%/year 2000 2005 Time 55%/year Gap Processor
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Memory density
Skills: center of gravity
USA: processors (Intel, Motorola, TI, ) Japan: memory (NEC, Toshiba, ) Future: IC = processor + memory Where???
Memory density grows faster than needs

1983: 512 Kbyte @ 64 Kbit/chip = 64 chips/PC 2001: 256 Mbyte @ 512 Mbit/chip = 4 chips/PC Compensated if you sell at least 16 times more PCs or if you find new applications (UMTS, car,) 2010: 4 Gbyte @ 64 Gbit/chip = 0.5 chip/PC No need for such a large memory chip unless you find new applications (3D video)
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Power consumption
Power (W/cm2) 1K 100
Hot plate P P Pro P II Nuclear reactor
10
386 486
P III
P4
1
1.5m 1m
0.7m
0.5m
0.35m 0.25m 0.18m 0.13m
0.1m Line
width
Processor architecture design driven by memory bottleneck & power problem! Nevertheless, cooling tower is necessary!
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Fred Pollack, Keynote at Micro99
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Power consumption
Cooling tower
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Power consumption
Let us do a calculation:
How long could a GSM using a Pentium 3 (hardly powerful enough) last on a single battery charge? Capacity of a battery: 600 mAh @ 4V = 2400 mWh Power consumption Pentium 3: 45 W One charge lasts for 3 minutes!!! We want a GSM to last for 240 hours on a single charge. How much power may be consumed by the processor? Capacity of a battery: 600 mAh @ 4V = 2400 mWh Power consumption processor: 10 mW Possible via specialization to the application: dedicated hardware
Let us turn the computation upside down:
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Summary on technological trends

Technologically speaking, we can have the same exponential evolution for another decade This gives us at least 4 decades of exponential evolution, never seen in history End-user price stayed the same or even decreased
Since 30 years, the price for a brand new processor is 1000 USD
So far for the good news
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Design issues
Performance 1M 100K 10K 1K 100 10 1 1980 1985 1990 1995 55%/year Gap Design complexity
Design productivity 10%/year Time

2000 2005
Unfortunately, Gordon Moores law is also valid for the design complexity, which doubles every 18 months
and worse, design productivity doubles only every 10 years
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Design issues
We can build exponentially complex circuits, but we cannot design them
Design of Pentium 4: 8 years, during last 2 years with a team of 1000 persons Who can afford this???
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Microcontrollers

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Gii thiu v vi iu khin

Vi iu khin = CPU + B nh + cc khi ghp ni ngoi vi + cc khi chc nng
EEPROM RAM ADC/DAC Timer B to xung nhp PWM UART USB ...
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Vi x l vs. Vi iu khin
Vi x l l mt CPU c s dng trong cc my tnh. Cc vi b iu khin v cc b vi x l c ba im khc nhau chnh sau:kin trc phn cng, phm vi ng dng, v c im tp lnh. Kin trc phn cng: Mt b vi x l ch l mt CPU n l trong khi mt b vi iu khin l mt IC cha CPU v cc mch ngoi vi chnh ca mt my tnh hon chnh (nh RAM, ROM, giao din ni tip, giao din song song, b nh thi, mch x l ngt) ng dng: Vi x l thng c dng nh mt CPU trong cc my tnh trong khi cc vi iu khin c s dng trong cc thit b nh iu khin cc hot ng.
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Vi x l vs. Vi iu khin
Tp lnh:
Tp lnh ca vi x l thin v x l d liu.
Chng c th lm vic vi 4 bit, byte, word, thm ch double word. Ch a ch cho php truy nhp cc mng d liu ln bng cch s dng con tr v a ch offset.
Tp lnh ca vi iu khin dng iu khin cc truy nhp vo v ra.

Chng c cc lnh cho php thit lp v xo cc bit ring r v thc hin cc thao tc vi bit. C cc lnh cho cc hot ng vo/ra, o thi gian cc s kin, cho php v thit lp cc mc u tin cho cc ngt ngoi.
Kh nng x l ca vi iu khin thp hn rt nhiu so vi vi x l.

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Microcontroller facts
99% processor market Shipments- > 16 Billion in 2000, 8 bit > 1/2 market Major Players: Microchip 16Fxx, Intel 8051, Motorola MC68HC05, National COP800, SGS/Thomson ST62, Zilog Z86Cxx
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Motorola MC68331
2 Timers 1 12 7 Serial asynch. Buffered I/O Programmable chip selects 32 bit integer CPU FT unit: watchdog clock&bus monitor 16 data
24
address
Interrupt logic
Clock frequency: > 16 MHz MC683xx: modular microcontroller unit: MC68000 core plus customized peripherals
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Motorola MC68332
Timer PU 1 12 7 Serial asynch. Buffered I/O Programmable chip selects 32 bit integer CPU FT unit: watchdog clock&bus monitor 2 Kbyte RAM 16 data
24
address
Interrupt logic
48 Parallel I/O
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Motorola MC68340
2 Timers 2 4 7 Serial asynch. I/O Programmable chip selects 32 bit integer CPU FT unit: watchdog clock&bus monitor 2 channel DMA controller 16 data
32
address
Interrupt logic
16 Parallel I/O
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Motorola MC68F333
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64 Kbyte on chip flash EEPROM 68020 processor 4 Kbyte SRAM 8 channel 10-bit ADC 16 channel 16-bit timer several interfaces Introduced in 1994
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Motorola MC68HC16
16-bit microprocessor Introduced in 1994

www.freescale.com
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Microcontrollers

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H vi iu khin 8051
Hin nay c hn 40 cng ty sn xut cc loi vi iu khin khc nhau ca h 8051. Mt s cng ty c trn 40 version 8051. Cc CORE 8051 c th c t hp trong cc FPGA hay ASIC. Trn 100 triu vi iu khin 8051 c bn ra mi nm. H 8051 gt hi c rt nhiu thnh cng v n cng trc tip nh hng n cu trc ca cc h vi iu khin hin nay.
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MCS-51
8051 thuc h vi iu khin MCS-51. MCS-51 c pht trin bi Intel v cc nh sn xut khc (nh Siemens, Philips) l cc nh cung cp ng th hai ca h ny. Tm tt mt s c im chnh ca h 8051:
4K bytes ROM trong 128 bytes RAM trong 4 cng I/O 8-bit 2 b nh thi 16 bit Giao din ni tip Qun l c 64K b nh code bn ngoi Qun l c 64K b nh d liu bn ngoi
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H vi iu khin 8051
Cc ngt ngoi Ram trong
Thanh ghi chc nng c bit
Cc s kin cn m
128 byte FF ram 80
iu khin ngt CPU
Ngun Ngt Trong
128 byte RAM
7F 00
B dao ng
Qun l Bus
Port 0
Port 1
Port 2
Port 3
Cng ni tip
XTAL 1,2
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PSEN ALE
a ch a thp/d ch cao
M rng trong 8032
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Tham kho
H vi iu khin 8051 www.atmel.com/products/8051/ http://chaokhun.kmitl.ac.th/~kswichit/ http://www.sunrom.com/
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Microcontrollers

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H vi iu khin AVR
Bus d liu 8 bt B nh flash 1k x 16 cho chng trnh B m chng trnh Trng thi v kim tra
Thanh ghi iu khin n v ngt n v SPI UART ni tip Timer/Counte r 8 bt
Thanh ghi lnh B gii m lnh
Thanh ghi a nng 32 x 8
ALU
Cc ng iu khin
128 x 8 Data SRAM 128x8 EEPROM
Timer/Counte r bit vi B16 nh thi PWM watchdog

B so snh analog 15 ng dn vo/ra
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Microcontrollers

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Gii thiu chung v PSoC

PSoC l g?
Do hng Cypress sn xut Mt loi cng ngh IC mi pht trin trong vi nm gn y. Kh nng tch hp ng cc loi linh kin s v tng t to ra cc khi s hoc tng t vi chc nng tu thuc ngi dng. Kt hp vi mt vi iu khin trung tm.
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Cu trc PSoC
Li PSoC Vi x l 8bit, 24MHz, 4MIPS Flash ROM (t 16K) RAM (128b-2kb) B iu khin ngt Bus Cc khI s Flip-Flop, cng logic Cc khI tng t Cc b khuch I thut ton in tr T in iu khin ng ngt Ti nguyn h thng c bit: Debugger core
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ng dng
X l tn hiu
Pht hin sng Sin o in p o tn s in ch/giI iu ch Lc Nhn tng t FSK
Giao tip vi cm bin

in tr nhit Cp nhit o tn hiu hng ngoI th ng Thu siu m o p sut
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So snh thit k gia VXL, VK, PSoC
ng dng: Mch o in p 0-5V, hin th gi tr ra LED

Thit k phn cng Thit k phn mm
Ngun in p
Tng t/S
B x l trung tm
Hin th LED
Ngun nui
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So snh
Vi x l phc tp phn cng Gi thnh n nh Kh nng pht trin h thng Cao Cao Thp Kh Vi iu khin Trung bnh Trung bnh Trung bnh Trung bnh PSoC Thp Trung bnh Cao D
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Thit k h thng s dng PSoC

Chun b
IC Chng trnh thit k: PSoC Designer Chng trnh np v mch np
Cc bc thit k PSoC s dng PSoC designer

Thit k cng
La chn linh kin a vo cc khI s, tng t a cc linh kin vo cc khI v kt nI Thit lp cc thng s
Lp trnh
Kch hot cc linh kin: Component_Start() Vit cc thut ton s dng linh kin Vng lp v tn
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Mt s linh kin
ADC (6-14 bit) DAC (6-9 bit) Khuch I DTMF B lc (thng thp, thng dI) B m, b nh thI (8-24 bit) Dn knh: s+tng t Cc linh kin s: I2C, UART, giao tip LCD, m CRC, m gi ngu nhin, giao tip chun thu /pht hng ngoi
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Chn linh kin
Linh kin trong h thng Ti nguyn h thng Chn linh kin Hng dn s dng linh kin
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Thit k
Thng s chung Thng s linh kin
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Tng t
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Lp trnh
Qun l theo d n
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Microcontrollers
Vi iu khin ca Motorola H vi iu khin 8051 H vi iu khin AVR PSOC iu khin trong cng nghip PLC Xu hng pht trin

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PLC (Programmable Logic Controller)

PLC = CPU + giao din vo ra c im ca PLC:
Gi thnh hp l cho cc ng dng iu khin phc tp Chu c rung ng, nhit, m, ting n v c bn cao C sn giao din cho cc thit b vo v thit b ra Lp trnh d dng vi ngn ng lp trnh n gin, ch yu gii quyt cc php ton logic v chuyn mch
PLC c dng ch yu iu khin trong cng nghip:

iu iu iu iu khin khin khin khin bng chuyn thang my my t ng: my khoan, my sy n giao thng
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Cu trc ca h thng PLC
B nh lu tr
chng trnh
Tn hiu
vo
Giao din vo
PLC
Tn hiu ra
Giao din ra
Vi x l
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Cu trc bn ngoi
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Microcontrollers

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Trends for microcontrollers

Standard CPU core surrounded by peripherals taken from a vast library Single architecture line is whole family
different memory & on-chip peripherals for embedded applications Deterministic behavior
no caches, no virtual memory, but on-chip RAM no out-of-order execution delayed branch prediction
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Trends for microcontrollers

Word length as small as possible
4 bit: 2% 8 bit: 36% 16 bit: 25% 32 bit: 34% 64 bit: 3%
Not pushing the limits of performance for cost reasons
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Microcontrollers

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Texas Instruments TMS320C20x Low end consumer Fixed Point

Dual access data RAM PROM Loop controller fixed MAC 16x16+32->32 16 data
Selection of peripherals: serial comm., timers,...
18
address I/O 16 data 16 address

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Series continued; typical app.: Digital camera, feature-phones, disk drives, Point-of-Sales Terminal 40 MHz, 3.3-5V, 3LM Available as core
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Texas Instruments TMS320C24x Low end consumer Fixed Point

Dual access data RAM PROM Loop controller Selection of peripherals: serial comm., timers,... fixed MAC 16x16+32->32 8 output PWM 8 channel A/D CAN bus controller watchdog 16 data
16
address
Series continued; typical app.: electrical motor control 50 MHz, 5V
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Texas Instruments TMS320C3x Floating Point

XRAM YRAM PRAM 32 bit floating add 32 bit floating multiply ACU 32 data
24
Loop controller
ACU
Selection of peripherals: serial comm., timers, DMA, ...
Series discontinued; typical app.: speech, audio 60 MHz, 3.3-5V, 144 pin Super scalar
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Texas Instruments TMS320C4x Floating Point Message Passing

20 MB/s 4KByte XRAM 4KByte YRAM 8 PRAM 32 bit floating add 32 bit floating multiply ACU 32 data
32
address
Loop controller
12 channel DMA controller
ACU
32 data 32 address
Serial link, timers
Series discontinued; typical app.: prototyping, radar 60 MHz, 5V, 325 pin Super scalar; message passing multiprocessor
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Texas Instruments TMS320C54xx High end consumer Fixed Point

Dual access XRAM YRAM PROM Fixed ALU 32+32->40 Fixed Add 32+32->40 Fixed multiply 17x17->34 32 data
17
Loop controller
6 channel DMA controller Buffered serial links, timers, ...
Viterbi
ACU ACU
Series continued; typical app.: GSM, set-top box, audio 1.8-5V, max. 160 MHz, 144 pin, .15mm (1999), 0.32mW/MIPS for the core Specialized on-chip unit: will occur more often in future e.g. C5420: dual core + 2x100 MW on-chip SRAM 83 e.g. C5402: 5$ for 100 MIPS
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Texas Instruments TMS320C5510 High end consumer Fixed Point

Dual access XRAM (256 Kbyte) Fixed ALU 32+32->40
YRAM (64 Kbyte)

PROM 32 KByte P-cache 24 KByte Power Mgment 6 channel DMA controller
Fixed Add 32+32->40

Fixed multiply 17x17->34 Fixed multiply 17x17->34 Viterbi ACU
32
data
24 address I/O 16 data 16 address
Buffered serial links, timers, ...
ACU
Series continued; typical app.: UMTS handheld 1.6V, 200 MHz, .15mm (2000), 400 MIPS,0.05mW/MIPS (core), power management per unit and per cycle Specialized on-chip unit: will occur more often in future 84
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Texas Instruments TMS320C8x Fixed Point Video

2 Kbyte RAM1 DSP processor 1 DSP processor 2 2 Kbyte RAM16 2 Kbyte I-cache1 Xbar DSP processor 3 DSP processor 4 2 Kbyte I-cache4 4 Kbyte D-cache 4 KByte I-cache 2 KByte RAM General purpose RISC processor Video controller Transfer controller 32
address
data 64
Series discontinued; typical app.: video phone, video conferencing, multimedia workstations Introduced: 1995, 50 MHz, 305 pin Multiprocessor-on-a-chip; sub-word SIMD for each DSP
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Texas Instruments TMS320C6201 High end Fixed Point

16KByte D-SRAM 16KByte D-SRAM 16KByte D-SRAM 16KByte D-SRAM 64KByte P-SRAM/cache JTAG / clock pump 4 channel DMA Ext. memory interface 2 Serial ports 2 Timers fixed MUL 16x16->32 fixed MUL 16x16->32 fixed ALU 32+32->40 fixed ALU 32+32->40 fixed ALU/branch 32+32->40 fixed ALU/branch 32+32->40 integer ACU 32+32 integer ACU 32+32 External memory 23
address
data 32
Host interface 17 address
data
16
86
Series continued; typical app.: modems, multimedia 1997, 0.25 mm, 5ML, 352 pin, 200 MHz, 2.5V, 1.9W, $85 Super scalar (8 Instr./cycle), 1600 MIPS VLIW: 256 bit instruction word
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2x16KByte D-RAM (Shadow load) 2x16KByte D-RAM (Shadow load) 2x16KByte D-RAM (Shadow load) 2x16KByte D-RAM (Shadow load) 2x128KB P-RAM (Shadow load) JTAG / clock pump 4 channel DMA Ext. memory interface 2 Serial ports 2 Timers fixed MUL 16x16->32 fixed MUL 16x16->32 fixed ALU 32+32->40 fixed ALU 32+32->40 fixed ALU/branch 32+32->40 fixed ALU/branch 32+32->40 integer ACU 32+32 integer ACU 32+32 External memory 23?
address
data 32
Expansion bus 17? address
data
32
87
Series continued; typical app.: modems, multimedia 1999, 0.18 mm, 5ML, 352 pin, 250 MHz, 1.8V, 1.9W, $130 Super scalar (8 Instr./cycle), 2000 MIPS, scales well till 700 MHz (6000 MIPS) Optimum choice when all data fits in on-chip memory
DHBK 2005

2x64KByte D-RAM (Shadow load) 2x64KByte D-RAM (Shadow load) 2x64KByte D-RAM (Shadow load) 2x64KByte D-RAM (Shadow load) 256KByte P-RAM 128KB P-cache/RAM JTAG / clock pump 4 channel DMA Ext. memory interface 2 Serial ports 2 Timers fixed MUL 16x16->32 fixed MUL 16x16->32 fixed ALU 32+32->40 fixed ALU 32+32->40 fixed ALU/branch 32+32->40 fixed ALU/branch 32+32->40 integer ACU 32+32 integer ACU 32+32 External memory 23?
address
data 32
Expansion bus 17? address
data
32

88
Series continued; typical app.: base stations 2000, 0.15 mm, 5ML, 18 mm2 package size, 300 MHz, 1.5V, 1.5W Super scalar (8 Instr./cycle), 2400 MIPS Optimum choice when all data fits in on-chip memory
DHBK 2005

4KByte L1 Dcache (2 way set assoc.) 4KByte L1 Pcache (2 way set assoc.) 4x16KByte L2 cache (direct map) fixed MUL 16x16->32 fixed MUL 16x16->32 fixed ALU 32+32->40 fixed ALU 32+32->40 fixed ALU/branch 32+32->40 fixed ALU/branch 32+32->40 integer ACU 32+32 integer ACU 32+32 External memory 30
address
data 32
JTAG / clock pump 16 channel DMA Ext. memory interface 2 Serial ports 2 Timers
Host port 17 address
data
16
89
Series continued; typical app.: modems, multimedia 1999, 0.18 mm, 5ML, 256 pin, 150 MHz, 1.8V, 1.5W, $25 VLIW, 1.2 GIPS; cheap (25$ in 99, 5$ in 01) Optimum for random access to large memory space 80% of performance of C6x with infinite on-chip memory
DHBK 2005

16 Kbyte L1P direct mapped 16 Kbyte L1D 2way dual access 1 Mbyte RAM/L2 4way Dual EMIF & HPI & PCI & Utopia JTAG / clock pump 64 channel DMA 3 Serial ports 3 Timers Viterbi decoder accelerator Turbo decoder accelerator fixed MUL 16x16->32 fixed MUL 16x16->32 fixed ALU 32+32->40 fixed ALU 32+32->40 fixed ALU/branch 32+32->40 fixed ALU/branch 32+32->40 integer ACU 32+32 integer ACU 32+32 External memory 30 address data 64 30 address data
16
HPI ? address
data
32
90
Samples June 2001, 0.12 mm, 6 LM, 532 pin, 400 MHz-600 MHz, 1.2V, starts at 95$ in volume Super scalar (8 Instr./cycle), 3200-4800 MIPS Sub-word (8bit or 16bit) parallelism Specialized instr.: Galois Field Mult, bit manipulation
DHBK 2005
Texas Instruments TMS320C6701 High end Floating Point

16KByte D-SRAM 16KByte D-SRAM 16KByte D-SRAM 16KByte D-SRAM 64KByte P-SRAM/cache JTAG / clock pump 4 channel DMA Ext. memory interface Serial interface 2 Timers Fixed/Float MUL 32x32/64x64 Fixed/Float MUL 32x32/64x64 Fixed/Float ALU 32+32/64+64 Fixed/Float ALU 32+32/64+64 Fixed ALU/Branch Float 1/x & x Fixed ALU/Branch Float 1/x & x integer ACU 32+32 integer ACU 32+32 External memory 23
address
data 32
data
16
91
Series continued; typical app.: video compression Introduced: 1998, 0.18 mm, 5ML, 352 pin, 167 MHz, 1.8V Super scalar (8 Instr./cycle); VLIW; 1 GFLOP Foreseen for 00: 50$ (cf. C6211) & 3 GFLOP (cf. C6202)
DHBK 2005
Texas Instruments TMS320C6711 High end Floating Point

4KByte L1 Dcache (2 way set assoc.) 4KByte L1 Pcache (2 way set assoc.) 4x16KByte L2 cache (direct map) Fixed/Float MUL 32x32/64x64 Fixed/Float MUL 32x32/64x64 Fixed/Float ALU 32+32/64+64 Fixed/Float ALU 32+32/64+64 Fixed ALU/Branch Float 1/x & x Fixed ALU/Branch Float 1/x & x integer ACU 32+32 integer ACU 32+32 External memory 23
address
data 32
JTAG / clock pump 4 channel DMA Ext. memory interface Serial interface 2 Timers
data
16
92
Series continued; typical app.: video compression 2000, 0.18 mm, 5ML, 256 pin, 100 MHz, 1.8V, 2W, $20 VLIW, 600 MFlops Optimum for random access to large memory space 80% of performance of C6x with infinite on-chip memory
DHBK 2005
Texas Instruments
TMS320C541 (1995)
93
DHBK 2005
Texas Instruments
TMS320C545 (1995)
94
DHBK 2005
Texas Instruments
TMS320C80 (1994)
95
DHBK 2005

Microcontrollers

96
DHBK 2005
Motorola MC56xxx Audio Fixed Point

XRAM YRAM PRAM 16 or 24 bit integer CPU ACU ACU Selection of peripherals: ADC, DAC, comm., timers, PIO, ... 24 data
18
address
Loop controller
24 bit for audio: 16 bit data + overflow
97
DHBK 2005
Motorola MC56002
98
DHBK 2005
Motorola MC56166
99
DHBK 2005

Microcontrollers

100
DHBK 2005
Philips VSP-1 Fixed Point Video

12 512x12 bit Memory element 512x12 bit Memory element 10x18 cross-bar 10 12 bit integer ALU 12 bit integer ALU 12 bit integer ALU 12
12 bit for video: 8 bit data + overflow Clock Frequency: 27 MHz 1 instruction per sample period for HDTV, 2 instructions per sample period for TV
101
DHBK 2005

Inputs
ALU
ALU
ALU
ME
ME
Outputs
102
DHBK 2005
Output FIFOs
206K Transistors 1.1W dissipation 27 MHz clock 176 pin Introduced in 1991
Memory Element
103
ALU
DHBK 2005

12 512x12 bit Memory element1 512x12 bit Memory element2 12 bit integer ALU1 12 bit integer ALU2 12 512x12 bit Memory element4 22x50 cross-bar 22 12 bit integer ALU12
12 bit for video: 8 bit data + overflow Clock Frequency: 54 MHz 2 instructions per sample period for HDTV, 4 instructions per sample period for TV
104
DHBK 2005
105
1.15 M Transistors 5W dissipation 54 MHz clock frequency 208 pin Introduced in 1994
DHBK 2005
Sony Graphics Engine

Playstation 3
Status: prototype in 2001 287.5 MTOR 256 Mbit on-chip embedded DRAM 2000-bit wide internal bus 462 mm2 180 nm CMOS
106
DHBK 2005

Microcontrollers

107
DHBK 2005
Trends for DSP processors

No new generations that replace old generations, but multiple co-existing architecture lines Word length application dependent
Automotive: 16-bit fixed point (e.g. C2x) Speech: 32-bit floating point (e.g. C30) Audio: 24-bit fixed point (e.g. MC56K) Telecommunications: 16-32 bit fixed point (e.g. C5x, C6x) Video: 12-32 bit fixed point (e.g. C8x)
Single architecture line is whole family

different memory & on-chip peripherals for embedded applications (cf. microcontrollers)
108
DHBK 2005
Trends for DSP processors

Deterministic behavior
no caches, no virtual memory, but on-chip RAM banks no out-of-order execution delayed branch prediction
Increasing address space: 12 -> 32 Multiple functions on single chip: CPU, FPU, multiple RAM banks, ACUs, loop controller, ADC, DAC, PWM, serial interfaces, Often provisions for parallel processing
109

Microprocessor Final Ver1 Part7

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DHBK 2005

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Introduced: 1978 Clock frequency: 8 - 10 MHz

Intel Pentium Pro

Intel Pentium III

Dynamic branch prediction unit

Dynamic branch prediction unit

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Trends for general purpose processors

The future: general characteristics

10 0.5 183 0.4

Besides and beyond silicon (e.g. polymer electronics)

Besides and beyond silicon: applied to future ambient intelligent environments

Emile Aarts, HomeLab, Philips

Besides and beyond silicon: applied to future ambient intelligent environments

Emile Aarts, HomeLab, Philips

Besides and beyond silicon: applied to ambient intelligent HomeLab (2002)

Emile Aarts, HomeLab, Philips

The future: high performance (mP)

CTO Intel says in 2001

1.8 GTOR in 2010

The future: high performance (mP)

(Gordon Moore, founder Intel Corp.)

Smaller capacitors => faster

Enables new applications

The future: DRAM

Memory density grows faster than needs

0.35m 0.25m 0.18m 0.13m

Fred Pollack, Keynote at Micro99

Let us turn the computation upside down:

Summary on technological trends

So far for the good news

Design productivity 10%/year Time

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Gii thiu v vi iu khin

Tp lnh ca vi iu khin dng iu khin cc truy nhp vo v ra.

Kh nng x l ca vi iu khin thp hn rt nhiu so vi vi x l.

16-bit microprocessor Introduced in 1994

Chng 7: Cc b vi x l trn thc t

Digital signal processors

iu khin ngt CPU

Ngun Ngt Trong

128 byte RAM

M rng trong 8032

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Thanh ghi iu khin n v ngt n v SPI UART ni tip Timer/Counte r 8 bt

Thanh ghi lnh B gii m lnh

Thanh ghi a nng 32 x 8

128 x 8 Data SRAM 128x8 EEPROM

Timer/Counte r bit vi B16 nh thi PWM watchdog

Chng 7: Cc b vi x l trn thc t

Digital signal processors

Gii thiu chung v PSoC

Giao tip vi cm bin

So snh thit k gia VXL, VK, PSoC

ng dng: Mch o in p 0-5V, hin th gi tr ra LED

Thit k h thng s dng PSoC

Cc bc thit k PSoC s dng PSoC designer