FPGA & ITS ARCHITECTURE

THE FUTURE PROGRAMMABLE IC

OUTLAY

Field-Programmable Devices. Types of Field-Programmable Devices.

The Evolution Of FPGA.

Types of FPGA. FPGA ARCHITECTURE (XILINX SPARTAN-II).

Field-Programmable Logic Devices

A Field-Programmable device is a programmable IC. Unlike traditional application-specific integrated circuit (ASIC), function is specified by the user after the device is manufactured. It can be programmed by users to implement circuit designs at their own sites. Instant manufacturing (in minutes) at users site.
3

Types of Field-Programmable Logic Devices

FPGAs
Field-Programmable Gate Arrays

CPLDs
Complex Programmable Logic Devices

SPLDs
Simple Programmable Logic Devices
4

Simple Programmable Logic Devices (SPLD)

An SPLD is a lot of gates with interconnects that can be programmed to form desired logic functions. There are two basic types of SPLDs:
The PLA : Programmable Logic Array The PAL : Programmable Array Logic
5

Programmable Logic Array ( PLA )

The PLA has both a programmable AND array & a programmable OR array.

Programmable Array Logic ( PAL )

The PAL has a programmable AND array with a fixed OR array

Complex Programmable Logic Devices (CPLD)

An CPLD is formed by joining of two or more SPLDs on a single IC using an interconnect.

FPGA

Field-Programmable Gate Array Evolution

Introduced in 1985 by Xilinx.

Consists of an two-dimensional array of programmable logic blocks.

9

FPGA = FP + GA
Field Programmable means that the FPGAs function is defined by the users program rather than by the manufacturer of the device. Gate Array means it consists of an array of gates which can be connected according to the requirements of the logic to be implemented.
10

Field-Programmable Gate Array (FPGA)

An array of programmable logic blocks connected with programmable interconnects. A device in which the logic structure can be directly configured by the end user without the use of an IC fabrication facility. A device who's function is specified by the user after the device is manufactured. FPGAs can have medium-to-high capacity(equivalent to that of thousands to millions of logic gates). Speed: up to 200MHz or more.
11

Types of FPGA
Broadly we can divide FPGAs into three types: 1. Antifuse FPGA 2. Flash FPGA 3. SRAM FPGA

12

Antifuse FPGA
Devices are configured by burning a set of fuses. Once the chip is configured, it cannot be altered any more. Hence only one-time programmable. Its logic cells are made up of conventional logic gates. Used for ASIC replacement for small volumes.
13

Antifuse FPGA
How to make a permanent short connection ?

14

Flash FPGA
Devices may be re-programmed several thousand times and are non-volatile, i.e. keep their configuration after power-off. With only marginal additional effort, the chips may be updated in the field. Re-configuration takes several seconds.

15

Static RAM FPGA

Currently the dominating technology. Unlimited re-programming. Additional circuitry is required to load the configuration into the FPGA after power on. Re-configuration is very fast, some devices allow even partial re-configuration during operation. Allows new approaches & applications like , Reconfigurable Computing.
16

FPGA ARCHITECTURE

ARCHITECTURE of XILINX SPARTAN-II FPGAs

17

Basic Spartan-II Block Diagram

18

Structure of a FPGA

19

FPGA Architecture Building Blocks

Configurable Logic Block (CLB)

Programmable Interconnection Network Programmable Input / Output Block(IOB)

20

Configurable Logic Block (CLB)

Configurable Logic Block (CLB) Logic Cell (LC). Look-Up Tables (LUTs) Multiplexers Flip-flops and latches

The basic building block of the CLBs is the logic cell(LC). Each CLB contains four LCs, organized in two similar slices.Each slice contains two LCs .
21

Logic Cell (LC)

An LC includes a 4-input function generator(Look-Up Table), carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop.

22

Look-Up Table
Any functions of up to K variables can be implemented by a single K-input LUT. The function generators are implemented as 4-input look-up tables (LUTs) in XILINX SPARTAN-II FPGAs. Each LUT can provide a 16x1-bit synchronous RAM. The two LUTs within a slice can be combined to create a 16x2-bit or 32x1-bit synchronous RAM.
23

Look-Up Table Implementation

Example : 2 - LUT Example : 4 - LUT

24

25

Additional Logic
Storage Element : Either edge-triggered D-type flip-flop
or level-sensitive latch. SR : Synchronous Set/Reset signal.It forces FF into its initialize state as specified in the configuration. BX / BY G1-4 / F1-4 : Forces to opposite state. : Inputs of the LUT.

CE
CLK

: Clock enable signal.

: Clock signal.
26

Additional Logic
F5 Multiplexer : It combines the function generator o/p.Used to implement 5 i/p function & select function up to 9 inputs.

F6 Multiplexer

: Used to implement 6 i/p function or

8:1 Mux. Select function up to 19 I/p

can be implemented.
CIN XOR Gate AND Gate : Carry i/p is present in each slice. : Allows 1-bit full adder implementation. : Improves efficiency of multiplier implementation .
27

Usage of F5 and F6 Multiplexer

28

Programmable Interconnection Network

Programmable Interconnection Network

Switch matrices Line segments

29

Programmable Interconnection Network

30

Programmable Interconnection Point (PIP)

Two types of PIPs in each switch matrix
Buffered

PIP

Pass transistor + buffer

Connected to longer wires

Faster
Unbuffered

PIP

Only pass transistor Connected to shorter wires Less area

31

Line Segments
Connectable Pair (A,B)
PIP between them in FPGA Non-connectable Pair (C,D) No PIP between them

32

Programmable Interconnection Point

Not every pair connectable. e.g. no PIP between (N1,S3)

33

Programmable Input/Output Block (IOB)

Programmable Input / Output Block

Input/Output Pads Input Path Logic Output Path Logic

34

Input/Output Block (IOB)

35

Input/Output Block (IOB)

IOB Register(T,O,I) : Either edge-triggered D-type flip
flop or level-sensitive latch. CLK : Each IOB has clock signal shared by the three registers. CE : Each register have a independent

clock enable signal.

SR : Synchronous Set/Reset signal.It forces FF into its initialize state as specified in the configuration.
36

Input/Output Block (IOB)

Input Path : A buffer in i/p path routes the i/p signal
either directly or through optional flip-flop to internal logic. Output Path : The output path includes a 3-state output. buffer that drives the output signal onto the pad. The output high voltage depends on an externally supplied Vcco voltage.

(The optional delay element at the D i/p of flip-flop

eliminates pad-to-pad hold time)
37

References
www.xilinx.com http://www.em.informatik.uni-frankfurt.de/ http://crc.stanford.edu Logic and Computer Design Fundamentals, 2nd ed., Sections 6.5-6.9.

Programmable Logic Design: Quick Start Handbook, p.1-8.

Physical Design for FPGAs Rajeev Jayaraman FPGAs become a mainstream ASIC alternative

Shelly Davis, Xilinx Portable Design Magazine ,July 19, 2001

The Spartan-II Family - The Complete Package Xilinx, Inc January 10, 2000Xilinx, Inc,March 9, 2000 Field Programmable Gate Arrays, Product Specification ,Xilinx, IncMay 14, 1999
38

THANKS
39