OpenRISC-Based Embedded

System Design

April. 3, 2007

Dynalith Systems www.dynalith.com

Agenda
Introduction to OpenCores OpenRISC Architecture OpenIDEA Example

Introduction

(2)

Introduction to OpenRISC
OpenRISC
Free open-source synthesizable RISC processor Distributed by OpenCores, http://www.opencores.org

OpenRISC 1000 (or1k)

Target
medium and high performance networking and embedded computer environments

Architecture
32/64-bit load/store RISC architecture Designed with emphasis on performance, simplicity, low power requirements and scalability

Architecture Definition
Instruction set, register set, cache management & coherency, memory model, exception model, addressing mode, operands conventions, application binary interface

Not define implementation-specific details

Pipeline depth, cache organization, branch prediction, instruction timing, bus interface

Reference: OpenRISC 1000 Architecture Manual

Introduction (3)

OR1K Architecture Overview

Address space 32-bit or 64-bit logical address space Simple and uniform-length instruction Different instruction set extensions - ORBIS 32/64 (OpenRISC Basic Instruction Set) 32-bit wide, operating on 32- and 64-bit data - ORDVX64 (OpenRISC Vector/DSP eXtension) 32-bit wide, operating on 8-, 16-, 32- and 64-bit data - ORFPX32/64 (OpenRISC Floating-Point eXtension) 32-bit wide, operating 32- and 64-bit data Separate instruction and data cache/MMU (Harvard architecture) Unified instruction and data cache/MMU (Stanford architecture) Addition of a register operand and a signed 16bit immediate Two source register operands (or one register and a constant) and one result register Branch delay slot for keeping the pipeline as full as possible Fast context switch support in register set, caches and MMUs

Instruction

Architecture Memory addressing Instruction operands Branch Context switch

Introduction

(4)

OpenRISC 1000 implementations

OR1200
Entry level 32bit RISC processor I/D Cache, I/D MMU, Tick timer, PIC, Debug Internet appliances, Networking, Handheld

OR1100
Entry level 32bit DSP I Cache, Tick timer, PIC, Debug VoIP, Modems, Imaging

OpenRISC 1000 architecture 32/64-bit

OpenRISC 1200 32/-bit

OpenRISC 1x00

OR1400
High performance superscalar 64bit RISC I/D Cache, I/D MMU, Tick timer, PIC, Debug, FPU, Vector/DSP Telecom, Home entertainment

OpenRISC

OR1500
A limited configuration SystemC implementation

How the implementation is configured Which features are implemented OpenRISC 1000 family

Introduction

(5)

OpenRISC 1200
An implementation of OR1K architecture
32-bit scalar RISC ORBIS32 instruction set Harvard micro-architecture Five-stage integer pipeline Virtual memory support (MMU)
Separated IMMU and DMMU

Performance
250 MIPS Dhrystone 2.1 @ 250Mhz wc 250 MMAC operations @ 250Mhz wc <500mW or <1W @ 250Mhz, 0.18mm <0.4mm2 @ 0.18mm 6LM (excluding cache & memory)

Separated I-cache and D-cache

Including Components
Debug unit Tick timer Programmable interrupt controller Power management

Introduction

(6)

OpenRISC 1200
L1 Caches
I/D Cache (1 to 8 KB) 1-way direct-mapped cache

MMU
With 1-way direct-mapped TLB Harvard model TLB, 16 to 64 entries

OpenRISC 1200
PM I/F DB I/F POWERM

System I/F

Power Management
Power save modes Software controlled clock frequency Interrupt wake-up Dynamic clock gating for individual units

IMMU WB I

DEBUG

ICache 8KB DCache 8KB WB I

Interrupt Controller
30 maskable interrupt sources

Tick Timer
TICK TIMER CPU/DSP
Task scheduling Time measurement Interrupt generation Single-run, restartable or continuous mode

INT I/F

PIC

DMMU

Debug Unit
JTAG Test Access Port Non-intrusive Realtime debug/trace for both CPU and System Accessible via development interface Links into GDB

Reference: OpenRISC 1200 IP Core Specification

Introduction (7)

OpenRISC 1200, Leon 2, MicroBlaze

Introduction

(8)

Architecture Details
Register Set Instruction Set Exception Model Memory Model Memory Management Cache Debug Unit Performance Counter Unit Power Management Timer/PIC Application Binary Interface

Introduction

(9)

Register Set
Register set
Thirty-two or sixteen 32/64-bit general purpose registers All other registers are special purpose registers User-level/supervisor-level register Multiple sets of GPRs (not implemented in or1200)
Special purpose registers

Group # 0 1 2 3 4 5 6 7 8 9 10

Description System control/status Data MMU Instruction MMU Data cache Instruction cache MAC unit Debug unit Performance counter Power management PIC Tick timer

Special-purpose registers
32 groups, up to 2048 registers in a group l.mtspr/l.mfspr instruction

11
12-23 24-31

Floating point unt

Reserved Custom unit

Reference: OpenRISC 1000 Architecture Manual

Introduction ( 10 )

Instruction Set
Simple and uniform-length instruction format ORBIS32 (or1200)
32-bit wide, 32-bit boundary aligned, 32-bit data operation 32-bit integer instructions Basic DSP instructions 32-bit load/store instructions Program flow instructions Special instructions

ORFPX64
32-bit wide, 32-bit boundary aligned, 64-bit data operation Double-precision floating-point instructions 64-bit load/store instructions

ORVDX64
32-bit wide, 32-bit boundary aligned, 8-, 16-, 32-, 64-bit data operation Vector instructions DSP instructions

ORBIS64
32-bit wide, 32-bit boundary aligned, 64-bit data operation 64-bit integer instructions 64-bit load/store instructions

Reserved opcodes for custom instructions

ORFPX32
32-bit wide, 32-bit boundary aligned, 32-bit data operation Single-precision floating-point instructions

Introduction

( 11 )

Instruction Set
Or1200 Implementation Arithmetic/ logical
l.add/l.addc/l.addi l.sub l.mul/l.Mulu l.and/l.andi l.or/l.ori l.rori l.sll/l.slli/l.sra/l.srai/l.srl/l.srli l.xor/l.Xori

prefix

instruction

postfix

Branch

l.bf/l.bnf l.j/l.jal/l.jalr/l.jr l.Rfe l.lbs/l.lbz/l.lhs/l.lhz/l.lws/l.lwz l.sb/l.sh/l.sw l.sfeq/l.sfne l.sfges/l.sfgeu/l.sfgts/l.sfgtu l.sfles/l.sfleu/l.sflts/l.sfltu l.mfspr/l.mtspr l.movhi l.trap/l.sys

Load /Store Flag

Precision/data width d : double s : single b : byte h : half-word n : nibble Instruction Instruction set l : ORBSIS lf : ORFPX lv : ORVDX

Register Exception

Etc.

l.Nop

Introduction

( 12 )

Exception Model
Reset vector
0x100

Bus error
Caused by a bus interface error Bus error

Instruction/Data page fault

Caused by access to an invalid virtual address Segmentation fault

Alignment
Caused by not aligned access Bus error

Range
Caused by not available register access

Introduction

( 13 )

Memory Model
Weakly ordered memory model
High performance memory system Responsibility for strict access ordering on programmer Memory synchronization instruction
l.msync : complete of all load/store operations before the RISC core continues

Or1200 implementation
Strongly ordered memory model

Atomicity
Atomic memory access instructions
l.lwa, l.swa

Or1200 implementation
Not intended for use in multiprocessor environments No support for coherency between local data cache and caches of other processors or main memory Write-through cache

Introduction

( 14 )

Memory Management
Support for implementation specific size of physical address spaces up to 35 address bits (32 GByte) Three different page sizes:
Level 0 pages (32 Gbyte; only with 64-bit EA) translated with D/I Area Translation Buffer (ATB) Level 1 pages (16 MByte) translated with D/I Area Translation Buffer (ATB) Level 2 pages (8 Kbyte) translated with D/I Translation Lookaside Buffer (TLB)

Address translation using one-, two- or three-level page tables Powerful page based access protection with support for demand-paged virtual memory Support for simultaneous multi-threading (SMT) OR1200 implementation
Only level 2 paging is implemented.

Introduction

( 15 )

Memory Management
OpenRISC 1000 Specification
32-bit implementation 64-bit implementation

Introduction

( 16 )

Memory Management
OR1200 implementation
Level 3 paging implemented 1-way direct mapped TLB
Virtual Page Number (VPN) 31 TLB Tag (13(12)-bit) 31 13 TLB Index (7(8)-bit; 64(128)-entry) 19(20) 13 12 Page Offset (13-bit; 8KB) 0

14(13)

0 V

31

13 swe sre uwe ure

0 ci

Tag (13(12)-bit)

Physical PN (19-bit)

TLB Translate Register 64(128) -entry 64(128) -entry

TLB Match Register

31 ? Physical Page Number (19-bit) Hit/Miss

13

12 Page Offset (13-bit)

Physical Address

Introduction

( 17 )

Cache
Cache
1-way direct-map Up to 8KB for each I/D cache

Cache control
Block prefetch Block flush Block invalidate Block write-back Block lock

Or1200 cache implementation

Write-through mode No support for coherency No prefetch No support for cache line lock

Introduction

( 18 )

Quick Memory
Quick memory
On-chip memory Unified I&D memory

GenPC

Virtual Addr.

I-MMU

Physical Addr.

I-Cache Inst. QMEM

Data BIU

LSU

Virtual Addr

D-MMU

Physical Addr

D-Cache

Store Buffer Data

Data BIU

Introduction

( 19 )

Debug Unit
Eight sets of debug value/compare registers Match signed/unsigned conditions on
instruction fetch EA load/store EA load/store data

Combining match conditions for complex watchpoints Watch-points can be counted by Performance Counters Unit Watch-points can generate a breakpoint (trap exception) Counting watch-points for generation of additional watch-points

Introduction

( 20 )

Debug Unit
Registers
DVR (Debug Value Register) DCR (Debug Control Register)
Compare target Compare condition

DMR (Debug Mode Register)

WP/BP setting Combination of conditions of DVRs

DWCR (Debug Watch-point Counter Register) DSR (Debug Stop Register)

Core stop condition

DRR (debug Reason Register)

OR1200 implementation
Breakpoint but no watchpoint

Introduction

( 21 )

Performance Counter Unit

Benefits
To improve performance by developing better application level algorithms, To better optimized operating system routines For improvements in the hardware architecture of these systems To improve future OpenRISC implementations To add future enhancements to the OpenRISC architecture. To help system developers debug and test their systems.

Performance counter
Eight counters Counting predefined events
Load/store/instruction fetch I/D-cache miss LSU/branch/instruction fetch/data dependency stall I/D-TLB miss Watch point

Not implemented in OR1200

Introduction

( 22 )

Power Management
Slow down
Support 0~15 clock frequency level Need external clock synthesizer

Power mode (dynamic clock gating, dynamic voltage scaling)

Normal mode Doze mode
All disabled (clock gating) except tick timer and PIC Enter normal mode by timer or interrupt

Sleep mode
All disabled (clock gating) and voltage down except PIC Enter normal mode by interrupt

Suspend mode
All disabled (clock gating) and voltage down Enter normal mode by reset

OR1200
Power manager implemented But no clock gating implemented

Introduction

( 23 )

Overall Blocks
I-MMU Physical Addr. I-Cache Inst. QMEM Virtual Addr. Physical Addr Store Buffer Data Inst. BIU

D-MMU

D-Cache

Data BIU

Virtual Addr GenPC

PIC Register File Freeze Timer

LSU Inst. Fetch ALU

Operand MUX Except Multiplier MAC

Power Manager

Control Logic (decode)

SPR Write-back MUX Debug Unit

Introduction

( 24 )

Configurable Features
Supporting FPGA Xilinx Altera On-chip memory

Instruction cache

1-way 512-bytes
1-way 4K-bytes 1-way 8K-bytes No

Data cache

1-way 4K-bytes

1-way 8K-bytes
No Instruction MMU 64-entry TLB 128-entry TLB No Data MMU 64-entry TLB 128-entry TLB No BIST RAM BIST No
Introduction ( 25 )

Configurable Features
Burst bus interface On Off

Bus retry count

WISHBONE

1~256
Prior to WISHBONE B.3 CAP (consecutive address burst) (prior to B.3) WISHBONE B.3

Divider Rotate Multiplier

On Off On Off Fast

Slow
Off MAC Multiplier On Off On Off
Introduction ( 26 )

Configurable Features
Clock divide Register file 1 or 2 or 4 Two port RAM Dual Port RAM Flip-flop based register Debug unit Trace buffer PIC HW break point On/Off # of DVR/DCR pair 0~7 On Off # of interrupt (2~31) Off No

Tick timer

64-entry TLB
128-entry TLB No

Qmem Store buffer

On Off Entry 4 or 8 No
Introduction ( 27 )

Custom Instruction
Reserved instructions for custom implementation
ORBIS32/64
Eight instructions are reserved l.cust1 ~ l.cust8

ORFPX64
Two instructions are reserved lf.cust1.d, lf.cust1.s

ORVDX64
Eight instructions are reserved lv.cust1 ~ lv.cust8

Custom instruction implementation

Add decode logic for the instruction (or1200_ctrl.v) Add processing logic for the instruction (or1200_alu.v)

Introduction

( 28 )

Development Tools

Development Tool
Compiler Binary utility C library Architecture simulator Debugger GUI

Name
gcc binutils newlib or1ksim gdb insight

Version
3.4.4 2.16.1 1.10.0 0.2.0 5.3 GNU compiler GNU binary utilities GNU C library Or100 ISS with peri. models GNU source level debugger GUI

Introduction

( 29 )

Operating System

Operating System
Linux uClinux RTEMS ecos

Name
Linux uClinux RTEMS ecos

Version
Kernel 2.4 2.0 4.5.0 2.0 Hard real-time OS

Introduction

( 30 )

Reference Platform/Example

Etc. SoC platform

Name orp_soc

Version SoC reference platform

Monitor program
MP3 decoder GUI examples

orpmon
mad-xess Microwindows Various simple examples MAD MP3 player porting

Introduction

( 31 )

Outline
Software Development with OpenIDEA
Software Development Architecture Simulation

Hardware Development with iNSPIRE-Lite Hardware/Software Co-Verification with OpenIDEA Verification Flow

Introduction

( 32 )

Software Development

Source Browser

Code Editor

Compiler Window

Introduction

( 33 )

Software Development
Platform
Windows 2000/XP

Target Processor
or1200

Code Editor
Source Browser Syntax Highlighting Syntax Checking Block Indent/Dedent/Folding Comment out/uncomment Line Number Find/Replace/Find in Files

Introduction

( 34 )

Software Development
Compiler
gcc 3.4.4

Utilities
binutil 2.16.1 make bin2c bin2hex bin2flash bin2srec

Newlib
1.10.0

Introduction

( 35 )

Software Development
Startup Code Link Script File

Introduction

( 36 )

Architecture Simulation Source-Level Debugging

OpenIDEA

ISS: Architecture Sim

Debug Windows Source-Level Debugger

Processor Model SRAM Model Flash Model Socket Peripheral Models C Models

Introduction

( 37 )

Source-Level Debugging

Source Browser

Register

Watch

Stack

Code

Debugger

Break Point

Introduction

( 38 )

Source-Level Debugging
Debugger
gdb 5.0

C Source-Level Debugging
Break Step Watch, etc.

Assembly-Level Debugging
Instruction Step Register View, etc.

Introduction

( 39 )

Architecture Simulation
Processor Architecture Exploration
Core MMU Cache, etc.

System-Level Simulation with Peripheral Models

Memory UART Ethernet VGA, etc.

Performance Profiling
Execution Log Memory Profile, etc.

Introduction

( 40 )

Agenda
Software Development with OpenIDEA Hardware Development with iNSPIRE-Lite
Automatic Hardware Composition Open-Source Library Simulation/Synthesis/Prototyping

Hardware/Software Co-Verification with OpenIDEA Verification Flow

Introduction

( 41 )

iNSPIRE
HDL HDL HDL HDL Simuilation Environment Synthesis & Mappnig (for FPGA) Cycle-Level & Transaction -Level Co-Simuilation Environment Library

EDIF EDIF EDIF

Integrated Design Environment for Hardware Development

Architecture Exploration Generation of
HDL Simulation Environment SystemC Simulation Environment Synthesis & FPGA Mapping Cycle-Level & Transaction-Level Co-Simulation Environment

Supporting Various Library

Introduction

( 42 )

Architecture-Wizard
LEGO-Brick-Like Hardware Composition
GUI-Based Hardware Composition Various IP Library
Open Source IP

Architecture Exploration
IP Properties

Introduction

( 43 )

Architecture-Wizard
Bus Generation
AMBA AHB AMBA APB WISBHBONE

Bus Architecture Exploration

Bus Architecture Address Map Priority, etc.

Introduction

( 44 )

IP Library
OpenCores Library
License (L)GPL OR1200 OR1200 Debug Audio Video Ethernet CAN DMA PS2, etc.

Dynalith Library
FLASH Controller SRAM Controller JTAG to USB, etc.

Introduction

( 45 )

IP Library
RTL Source Synthesis Script Example
Hardware Software

Introduction

( 46 )

Simulation/Synthesis
Simulation Environment
Simulation Synthesis Emulation Top Module Generation Simulation Model Connection
SRAM, SDRAM, UART, etc.

Simulation Script

Synthesis
Top Module Gereration Synthesis Script Synthesis Assist

FPGA P&R
FPGA Mapping Script P&R Assist

Introduction

( 47 )

Agenda
Software Development with OpenIDEA Hardware Development with iNSPIRE-Lite Hardware/Software Co-Verification with OpenIDEA
Debugger + ISS Debugger + ISS + HDL Simulator (SystemC) Debugger + ISS + HDL Simulator + FPGA Debugger + HDL Simulator (+ FPGA) Debugger + FPGA Prototyping Debugger + ASIC

Verification Flow

Introduction

( 48 )

1. SW Simulation
OpenIDEA (Debugger+ISS)
Software Development

OpenIDEA

ISS Profile/Log

Debug Windows Source-Level Debugger

Processor Model SRAM Model Flash Model Socket C Models UART Model Socket Hello World. Terminal

Introduction

( 49 )

2.1 HW/SW Co-Simulation (IP Verification)

OpenIDEA (Debugger+ISS) + Third Party HDL Simulator
IP Verification Device Driver Development

OpenIDEA

ISS Processor Model SRAM Model IP1 IP2 Socket C Models

HDL Sim.

Debug Windows Source-Level Debugger

Socket IP3

Introduction

( 50 )

2.2 HW/SW Co-Simulation (System-Level)

OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)
System-Level Co-Simulation

OpenIDEA

ISS Processor Model Socket

HDL Sim. BUS SRAM Model IP1 IP2

Debug Windows Source-Level Debugger

Socket C Models

IP3

Introduction

( 51 )

3 HW/SW Co-Simulation/Co-Emulation
OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)
System-Level Co-Simulation/Co-Emulation

OpenIDEA

ISS Processor Model Socket

HDL Sim. BUS PCI/USB

FPGA

Debug Windows Source-Level Debugger

SRAM Model Socket C Models

IP1 IP3

IP2

Introduction

( 52 )

4.1 HW Simulation with SW Debugging

OpenIDEA (Debugger) + Third Party HDL Simulator
HW/SW Co-Verification with Accurate Processor Model SW Debugging with HW Probing

OpenIDEA

HDL Sim.

Debug Windows Source-Level Debugger

Processor Model IP1 IP2 BUS Socket SRAM Model C Models IP3

Introduction

( 53 )

4.2 HW Simulation with SW Debugging(2)

OpenIDEA (Debugger) + Third Party HDL Simulator + FPGA Board (Dynalith)
HW/SW Co-Verification with Accurate Processor Model SW Debugging with HW Probing

OpenIDEA

HDL Sim. PCI/USB IP1 BUS Socket SRAM Model C Models

FPGA Board

Debug Windows Source-Level Debugger

Processor Model

IP2 IP3

Introduction

( 54 )

5. HW Prototyping SW Debugging
OpenIDEA (Debugger) + FPGA Board (Dynalith)
HW/SW Co-Verification with Source-Level Debugger and BILA (Built In Logic Analyzer) or ChipScope(Xilinx)

OpenIDEA

FPGA Board

Debug Windows Source-Level Debugger

Processor Model IP1 IP2 BUS PCI/USB JTAG SRAM Model IP3

Introduction

( 55 )

6. In Circuit Emulation (ICE)

OpenIDEA (Debugger) + Evaluation Board/FPGA Board (Custom)
In-Circuit Emulation Software Development with Real Platform

OpenIDEA OpenICE

ASIC Board / Custom FPGA Board ASIC/FPGA

Debug Windows Source-Level Debugger USB

Processor BUS JTAG SRAM Model

IP1 IP2 IP3

Introduction

( 56 )

Agenda
Introduction to OpenRISC Software Development with OpenIDEA Hardware Development with iNSPIRE-Lite Hardware/Software Co-Verification with OpenIDEA Verification Flow

Introduction

( 57 )

Hardware Design/Verification Flow

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

System-Level HW-SW CoVerification

RT-Level

System-Level RTL Verification

FPGA Prototyping Synthesis

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Post PnR Simulation

Introduction

( 58 )

IP Design and Verification

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System
Architecture Wizard

HDL Simulation
iNSPIRE HDL Simulator Simuilation Top DUV IP Generation Test-bench Driver/Phy/Mem ory Model

System-Level HW-SW CoVerification

RT-Level

System-Level RTL Verification

FPGA Prototyping Synthesis

Socket

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Post PnR Simulation

Introduction

( 59 )

IP Design and Verification

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

Co-Emulation (Acceleration)
iNSPIRE Architecture Wizard Generation Design Flow Wizard

System-Level HW-SW CoVerification

RT-Level

System-Level RTL Verification

FPGA Prototyping Synthesis

HDL Simulator Simuilation Top

FPGA Board FPGA DUV Driver/Phy /Memory

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Testbench

Proxy

IP

Post PnR Simulation

Introduction

( 60 )

System-Level HW/SW Co-Verification (RTL)

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

System-Level HW-SW CoVerification

RT-Level

2.1 HW/SW Co-Simulation

System-Level RTL Verification
OpenIDEA ISS Processor Model SRAM Model IP1 IP2 Socket C Models HDL Sim.

FPGA Prototyping Synthesis

Debug Windows Source-Level Debugger

Gate-Level

Socket IP3

Gate-Level Simulation PnR Static Timing Analysis

Post PnR Simulation

Introduction

( 61 )

System-Level HW/SW Co-Verification (RTL)

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

System-Level HW-SW CoVerification

RT-Level

4.1 HW Simulation with SW Debugging

System-Level RTL Verification
OpenIDEA HDL Sim.

FPGA Prototyping Synthesis

Debug Windows Source-Level Debugger Processor Model IP1 IP2 BUS Socket SRAM Model C Models IP3

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Post PnR Simulation

Introduction

( 62 )

System-Level HW/SW Co-Verification (RTL)

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

System-Level HW-SW CoVerification

RT-Level

4.2 HW Simulation with SW Debugging

System-Level RTL Verification

FPGA Prototyping Synthesis

OpenIDEA HDL Sim. PCI/USB IP1 BUS Socket SRAM Model C Models IP2 IP3 FPGA Board

Gate-Level

Debug Windows

Processor Model

Gate-Level Simulation PnR Static Timing Analysis

Source-Level Debugger

Post PnR Simulation

Introduction

( 63 )

System-Level HW/SW Co-Verification (RTL)

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System

System-Level HW-SW CoVerification

RT-Level

5. HW Prototyping with SW Debugging

System-Level RTL Verification

FPGA Prototyping Synthesis

OpenIDEA FPGA Board

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Debug Windows Source-Level Debugger

Processor Model IP1 IP2 BUS PCI/USB JTAG SRAM Model IP3

Post PnR Simulation

Introduction

( 64 )

System-Level HW/SW Co-Verification (Gate-Level)

RTL Design of Each IP Individulal IP Design & Verification Individulal IP Verification Using HDL Test-Bench IP Verification in System
Debug Windows Processor Model IP1 IP2 Source-Level Debugger BUS Socket SRAM Model C Models IP3

4.1 HW Simulation with SW Debugging

OpenIDEA HDL Sim.

System-Level HW-SW CoVerification

RT-Level

System-Level RTL Verification

FPGA Prototyping Synthesis

Gate-Level

Gate-Level Simulation PnR Static Timing Analysis

Post PnR Simulation

Introduction

( 65 )

OpenIDEA
OpenIDEA
Software Development Processor Architecture Simulation Source-Level Debugging

TM

OpenRISC Development Toolkit

In-Circuit Emulation
With ASIC Source-Level SW Debugging JTAG Connection to PC

ASIC

HW/SW Co-Emulation
With FPGA Prototype Board (iNCITE ) Source-Level SW Debugging Signal-Level HW Debugging Using BILA Fast USB 2.0 Connection to PC Various Peripherals Supporting

iNCITE

HW/SW Co-Simulation
With Third-Party HDL Simulator Source-Level SW Debugging Signal-Level HW Debugging

3rd-Party HDL Simulator

iNSPIRE-Lite
Graphical Architecture Composition Automatic Hardware Generation Various Open-Source Library

OpenIDEA OpenRISC SoC - . , / .

()
: 02) 556-0020 Fax: 02) 556-2252 E-mail: contact@dynalith.com http://www.dynalith.com

Design and verification steps using OpenIDEA

ISS-based software simulation
It uses OpenRISC ISS to run software and pure-functional hardware model for hardware.

ISS-HDL co-simulation
It uses OpenRISC ISS to run software and RTL hardware model running on top of HDL logic simulator.

HDL-based simulation
It uses a whole system including OpenRISC core running on top of HDL simulator and the core is controlled by debugger.

FPGA-based emulation
It uses OpenRISC core to run software and hardware blocks in FPGA.

Introduction

( 67 )

Recommended design and verification steps

1. ISS-based software simulation using OpenIDEA. 2. Building system hardware model using iNSPIRE-Lite. 3. ISS-HDL co-simulation using OpenIDEA and HDL simulator. 4. Building system hardware for FPGA using iNSPIRE-Lite. 5. FPGA-based emulation using OpenIDEA and iNCITE.

Introduction

( 68 )

UART example
Example system
OpenRISC 1200 processing core Memory controller UART (Universal Asynchronous Receive and Transmit) WISHBONE bus

The user application program will be loaded into the SSRAM after crosscompilation, and run by the OpenRISC processing core. The user application program simply controls the UART in order to get and put character data through the serial cable, which is connected through the Line Driver and UART.

Introduction

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