CAD for Nano CMOS

Analog Design
Soumya Pandit
Institute of Radio Physics and Electronics
University of Calcutta

Contact: soumya_pandit@ieee.org
Outline
 Introduction
 Design Complexity: Design Productivity Gap
 Silicon Complexity: Nano CMOS Challenges
 Frontiers of Analog CAD Researches
 Performance modeling techniques
 Analog circuit synthesis
 Topology design
 Conclusion

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Growth of Electronics

Evolution of transistor sizes and Evolution of the cost of a single

number/die [Source: Intel] transistor [Source: Intel]
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Design Complexity [ITRS-01,03,07]
 Increasing number of functionality: SOC

Processors Memory

Logic Analog

 New signal processing algorithms and system architectures.

 Larger design team: often requires different kind of expert
knowledge
 Silicon complexity: Nano CMOS challenges

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Analog Components
 Inputs of a system: Sensing circuits, signal conditioning/
 Outputs of a system: Receiving circuits.
 Data Converters.
 Time/Frequency Synchronizers.
 High-performance digital circuits

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Time-to-market
 Time required to get a product from the concept to the
marketplace.

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Design Gap

Cost of design is the greatest threat to continuation of semiconductor roadmap

[ITRS2007]
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Silicon Complexity [ITRS 2007]
 Refers to the impact of process scaling and the introduction
of new materials or device/interconnect architectures.
 Non-ideal scaling of device parasitics and supply/threshold
voltages.
 Coupled high-frequency devices and interconnects.
 Process variability.
 Manufacturing variability.
 Decreased reliability.

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Design Technology
 Includes conception, implementation and validation of
microelectronics-based systems.
 Elements of DT includes
 Tools: EDA tools
 Libraries: Standard cells, reusability
 Process characterization
 Structured methodologies
 The role of DT is to enable profits and growth of the
semiconductor industry via cost-effective production of
designs that fully exploit manufacturing capability.

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EDA
 A CAD resource is a sophisticated, computerized workstation
and software used to design IC chips.
 CAD tools
 CAD methodologies
 Reduce design time and manage design complexity
 In digital VLSI circuit design, EDA tools are enough
matured.
 Fully automated process from behavioral description to tape out.
 Lack of robust analog CAD tools
 SPICE circuit simulator
 Layout editing environments

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Design Effort

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Conventional AMS Design flow
Electrical Synthesis
Specifications
Schematic

Physical Synthesis

Layout

Feedback
Verification

Fabrication

Chip
Yield/Process data
Testing
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Top-Down AMS Design [IEEE.Proc 2000]
System Concept

System Design Simulation Verification

Architectural Design Simulation Verification

Backtracking and Redesign

Forward Progress
Cell Design Simulation Verification

Cell Layout Simulation Verification

System Layout Simulation Verification

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Testing
Hierarchical Analog Design
Specifications at level i Layout at level i

Level i

Topology Selection Verification

Redesign
Specification
Translation Extraction

Verification
Layout Generation

Level i + 1
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Specifications at level i + 1 Layout at level i + 1
Illustration
Functional Description (SFG) of the System

Analog Switch
Gain Transfer Gain
S1 D
A1 Fcn
Vx A2
S2 EN Vout

Gain C B
-1

Clock

High Level Topology Behavioral

Generation /Selection System Specs
Verification

Optimal High -level Topology of the System

OTA OTA
OTA
Voltage Voltage
CMOS Filter
Amplifier Amplifier
Switch Gm5,
Gm1, Gm7, Vou
Gm6, CL
Gm2 Gm8 t
Vx
OTA
Inverter
Gm3, Clock
Gm4

High-Level Specification Translation

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02.06.09 Specification parameters (voltage gain , bandwidth , output impedance etc )
of all synthesizable component -blocks (voltage amplifier , inverter , filter)
Optimization-based Strategy
Design
specifications

Initialize design Equation -

variables based

Performance
evaluation

Simulation-
New values of Cost function based
the design computation
variables

Optimization
No OK ?
Algorithm

Yes

Solution 16
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Hierarchical Modeling (IEEE Proc.2007)
 In any hierarchical approach behavioral models/performance
models are the bridge between different level in the hierarchy,
both top-down and/or bottom-up.
 A model is a conceptual representation of a system that you
want to realize (specification model) or that you have realized
(implementation model).
 Characteristics of good model
 Reasonable accuracy
 Fast to compute
 Low Construction time
 Behavioral models: Simulation and Verification.
 Parameterized Models: Synthesis and Optimization
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Illustration

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Utility in Hierarchical Analog Design
Functional Description (SFG) of the System

Analog Switch
Gain Transfer Gain
S1 D
A1 Fcn
Vx A2
S2 EN Vout

Gain C B
-1

Clock

High Level Topology Behavioral

Generation /Selection System Specs
Verification

Optimal High -level Topology of the System

OTA OTA
OTA
Voltage Voltage
CMOS Filter
Amplifier Amplifier
Switch Gm5,
Gm1, Gm7, Vou
Gm6, CL
Gm2 Gm8 t
Vx
OTA
Inverter
Gm3, Clock
Gm4

High-Level Specification Translation

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02.06.09 Specification parameters (voltage gain , bandwidth , output impedance etc )
of all synthesizable component -blocks (voltage amplifier , inverter , filter)
Polynomial Approximation
 Simplest approximation for a weakly non-linear characteristic.
 Least squares error optimization

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Piecewise Approximation
 Piecewise linear approximation
 Represent non-linear functions by piecewise linear segments.
 Linear approximation of non-linear curve over small regions.
 Dimensionality problem for multi-dimensional curves.
 Piecewise polynomial approximation
 Approximates the non-linear function in each piecewise region by a
polynomial.
 Each piecewise polynomial region is reduced using a model order
reduction technique.
 Reduced models are stitched together with scalar weight functions.

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PWP Illustration [Roychowdhury 2003]

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Validation

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Parameterized Models
 Analog performances as functions of specification parameters
of the circuit.
 Used for analog circuit synthesis.
 Two approaches
 Template-based approach.
 Regression-based approach

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Posynomial approach [Gielen 2003]

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Contd..

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Template-Free Approach

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CAFFEINE [McConaghy 2005,..]
 No requirement of a-priori from designer.
 Model itself evolves as part of GP optimization process.
 Model complexity and accuracy tackled by a multi-objective
optimization problem.

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Accuracy Complexity Trade-off

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LS-SVM- based Approach [Pandit 2009]

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Contd..

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Analog Circuit Sizing

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OPAMP Synthesis [Wolfe 2003]

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High-Level Sizing [Pandit PhD Thesis]

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Topology Design [Martens 2008]
 Selection before or after sizing
 Set of candidate topologies.
 Each topology is optimized and the best is selected.
 A particular topology is selected based upon designer’s experience or
some tool and then the selected topology is optimized.
 Selection during sizing
 Generic topology template-based approach
 Topology parameters related to performances and the generated
topology is optimized for performances.
 Top-down topology generation.
 Starts from functional description of the system.

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Selection & Sizing [Medeiro 1994]

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Template-based Approach [Tang 2006]
Generic Template

 Optimization Parameters
 Power
 Sensitivity
 Hardware complexity

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02.06.09 Selected topologies
Top-Down Approach [Pandit PhD Thesis]
Transfer function
model, desired
specifications

State space model generation

 Continuous time
ΔΣ modulator system.
Seed functional topology
 Generated
Performance estimation Generation of new functional
topology
topology optimized
No for sensitivity,
Specs met ?
relative power
consumption and
Yes

Implementation style specific

optimal topology generation
hardware complexity.
Behavioral simulation
No

Specs met in presence of

non-idealities ?

Yes
Optimal component-
level topology 38
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 Topology Generation

b2

b3

u(t) y(n)
1/s 1/s 1/s 1/s

f1 f2 f3 f4

DAC

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Results

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Summary
 Analog CAD tools are essential to cope up with the increased
system design complexity and time-to-market factors.
 Nano-scale CMOS design poses additional challenges on
automated analog design.
 Structured hierarchical analog design is the required design
methodology.
 Hierarchical modeling of analog behavior and performances
play an important role in implementing hierarchical design
methodology.
 Automated analog sizing and topology generation are two
important steps of analog design automation.

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