Figure 3-1 Standard Logic Symbols For The Inverter (ANSI/IEEE Std. 91 1984)

Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std. 911984).

Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 3–2 Inverter operation with a pulse input. Open file F0302 to verify inverter operation.

Figure 3–3 Timing diagram for the case in Figure 3–2.

Figure 3–4

Figure 3–5

Figure 3–6 The inverter complements an input variable.

Figure 3–7 Example of a 1’s complement circuit using inverters.

Figure 3–8 Standard logic symbols for the AND gate showing two inputs (ANSI/IEEE Std. 911984).

Figure 3–9 All possible logic levels for a 2input AND gate. Open file F0309 to verify AND gate operation.

Figure 3–10 Example of AND gate operation with a timing diagram showing input and output relationships.

Figure 3–11

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Figure 3–14 Boolean expressions for AND gates with two, three, and four inputs.

Figure 3–15 An AND gate performing an enable/inhibit function for a frequency counter.

Figure 3–16 A simple seat belt alarm circuit using an AND gate.

Figure 3–17 Standard logic symbols for the OR gate showing two inputs (ANSI/IEEE Std. 911984).

Figure 3–18 All possible logic levels for a 2input OR gate. Open file F0318 to verify OR gate operation.

Figure 3–19 Example of OR gate operation with a timing diagram showing input and output time relationships.

Figure 3–20

Figure 3–21

Figure 3–22

Figure 3–23 Boolean expressions for OR gates with two, three, and four inputs.

Figure 3–24 A simplified intrusion detection system using an OR gate.

Figure 3–25 Standard NAND gate logic symbols (ANSI/IEEE Std. 911984).

Figure 3–26 Operation of a 2input NAND gate. Open file F0326 to verify NAND gate operation.

Figure 3–27

Figure 3–28

Figure 3–29 Standard symbols representing the two equivalent operations of a NAND gate.

Figure 3–30

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Figure 3–32

Figure 3–33 Standard NOR gate logic symbols (ANSI/IEEE Std. 911984).

Figure 3–34 Operation of a 2input NOR gate. Open file F0334 to verify NOR gate operation.

Figure 3–35

Figure 3–36

Figure 3–37 Standard symbols representing the two equivalent operations of a NOR gate.

Figure 3–38

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Figure 3–40

Figure 3–41 Standard logic symbols for the exclusiveOR gate.

Figure 3–42 All possible logic levels for an exclusiveOR gate. Open file F0342 to verify XOR gate operation.

Figure 3–43

Figure 3–44 Standard logic symbols for the exclusiveNOR gate.

Figure 3–45 All possible logic levels for an exclusiveNOR gate. Open file F0345 to verify XNOR gate operation.

Figure 3–46 Example of exclusiveOR gate operation with pulse waveform inputs.

Figure 3–47

Figure 3–48 An XOR gate used to add two bits.

Figure 3–49 Basic concept of a programmable AND array.

Figure 3–50

Figure 3–51 The programmable fuse link.

Figure 3–52 The programmable antifuse link.

Figure 3–53 A simple AND array with EPROM technology. Only one gate in the array is shown for simplicity.

Figure 3–54 Basic concept of an AND array with SRAM technology.

Figure 3–55 Setup for programming a PLD in a programming fixture (programmer).

Figure 3–56 Programming setup for reprogrammable logic devices.

Figure 3–57 Examples of design entry of an AND gate.

Figure 3–58 Simplified illustration of insystem programming via a JTAG interface.

Figure 3–59 Simplified block diagram of a PLD with an embedded processor and memory.

Figure 3–60 Typical dual inline (DIP) and smalloutline (SOIC) packages showing pin numbers and basic dimensions.

Figure 3–61 Pin configuration diagrams for some common fixedfunction IC gate configurations.

Figure 3–62 Logic symbols for hex inverter (04 suffix) and quad 2input NAND (00 suffix). The symbol applies to the same device in
any CMOS or TTL series.

Figure 3–63

Figure 3–64 The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.

Figure 3–65 The partial data sheet for a 74LS00.

Figure 3–66 The partial data sheet for a 74HC00A.

Figure 3–67 The effect of an open input on a NAND gate.

Figure 3–68 Troubleshooting a NAND gate for an open input.

Figure 3–69 Troubleshooting a NOR gate for an open output.

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Figure 3-1 Standard Logic Symbols For The Inverter (ANSI/IEEE Std. 91 1984)

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Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std. 91­1984).

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Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std. 911984).