N CU TRC MY TNH LAB 4: MIPS PIPELINED CPU

NGUYN THNH I

NGUYN CNG LINH

L HU V Nhm Khoa Trng : 37 : in T - Vin Thng : i Hc Bch Khoa Nng

I. XY DNG DATAPATH C BN 1. GII THIU YU CU CA LAB 4

Thit k chip MIPS Pipelined 32 bit thc hin c cc lnh: ADD,BNE,J,JR,LW,SW,SLT,SUB,XORI.

TP LNH

ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt]. BNE rs, rt, imm16: if (Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(Imm16)<<2 else PC = PC + 4. J target: PC = { PC[31:28], target, 00 } JR rs: PC = Reg[rs]. LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)]. SLT rd, rs, rt: If (Reg[rs] < Reg[rt]) Reg[rd] = 00000001(16) else Reg[rd] = 0000000016. SUB rd, rs, rt: Reg[rd] = Reg[rs] Reg[rt]. SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt]. XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR Zero_ext(Imm16).

2. CC KHI C BN
1. Khi tm v ly lnh: - Gm c: + B nh lnh (Instruction memory) + Thanh ghi PC (Program Counter) + B cng (Adder)

A.

KHI TM V LY LNH

B.

FILE THANH GHI 32 BIT (REGFILE)

C.

B ALU

D.

B NH D LIU

3. GHP NI V B SUNG DATAPATH

i vi cc lnh khun dng R: + Gm ADD, SUB, SLT v JR. Cc lnh ADD, SUB, SLT yu cu: Ly d liu t RegFile, a sang khi ALU tnh ton, lu li vo RegFile. + Ring lnh JR th ch cn ly d liu t RegFile thay i thanh ghi PC

3. GHP NI V B SUNG DATAPATH

i vi cc lnh khun dng R:

3. GHP NI V B SUNG DATAPATH

Thm lnh XORI:

XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR Zero_ext(Imm16)

Cn b sung: Khi Zero_extend B Mux chn u vo cho ALU

(ReadData2 hoc Zero_ext(Imm16) )

B Mux chn a ch cho WriteRegister(rd hoc rt )

3. GHP NI V B SUNG DATAPATH

Thm cc lnh truy cp b nh LW , SW:

- LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)]. - SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt].

Cn thm khi m rng du Sign_extend Thm b Mux chn gi tr cho WriteData : Ly kt qu t ALU hoc t DataMem

3. GHP NI V B SUNG DATAPATH

3. GHP NI V B SUNG DATAPATH

Thm cc lnh nhy: - Nhy c iu kin: BNE - Nhy khng iu kin: J, JR

PC = PC +4

THM LNH BNE (BRANCH IF NOT EQUAL)

THM LNH JUMP

THM LNH JR

4. KHI IU KHIN (CONTROL)

To ra cc tn hiu iu khin: - RegWrite - MemWrite - RegDst - MemtoReg - ALUSrc - Branch - ALUOp - Jump - MemRead - SignZero

Instruction

Opcode Op 5 Op 4 Op 3 Op 2 Op 1 Op 0 Jump RegDst ALUSrc MemtoReg

R-type 0 0 0 0 0 0 0 1 0 0 1

Lw 1 0 0 0 1 1 0 0 1 1 1

Sw 1 0 1 0 1 1 0 X 1 X 0

Bne 0 0 0 1 0 1 0 X 0 X 0

jmp 0 0 0 0 1 0 1 X X X 0

Xori 0 0 1 1 1 0 0 0 1 0 1

Input

Outputs

RegWrite

MemRead
MemWrite Branch ALUOp SignZero

0
0 0 10 X

1
0 0 00 0

0
1 0 00 0

0
0 1 01 0

0
0 X XX X

0
0
20 0

11 1

BNG GI TR TN HIU IU KHIN KHI ALU CONTROL

ALUOp Intruction LW ALUOp1 0 ALUOp2 0 F5 X F4 X Funct F3 X F2 X F1 X F0 X ALUControl 0 0

SW
BNE ADD XORI SUB SLT

0
0 1 1 1 1

0
1 0 1 0 0

X
X 1 X 1 1

X
X 0 X 0 0

X
X 0 X 0 1

X
X 0 X 0 0

X
X 0 X 1 1

X
X 0 X 0 0

0 0
1 0 0 0 0 1 1 0 1 1

21

JRCONTROL V BNECONTROL
JRControl: - Nu ALUOp = 10 (R-type) v Function = 001000 th JRControl = 1. Cn ngc li th JRControl = 0 bneControl - Nu Branch = 1 v ZeroFlag = 0 th bneControl=1 cn ngc li bneControl = 0

II. GII THIU V MIPS PIPELINE :

Pipeline : Cc lnh thc hin theo kiu gi u => Tn dng khong thi gian ri gia cc cng on ( Stages).

MT S XUNG T (HAZARD) TRONG CU TRC

PIPELINE

Structural hazard: - L xung t xy ra khi phn cng khng h tr vic kt hp x l cc lnh ng thi (vd:Khi 2 lnh lin tip cng ghi kt qu vo 1 thanh ghi,khi 2 lnh cng truy cp b nh cng 1 thi im).

MT S XUNG T (HAZARD) TRONG CU TRC

PIPELINE

Data hazard: - Xy ra khi m d liu cn cho lnh tip theo cha c sn v ang c x l cc lnh trc .

MT S XUNG T (HAZARD) TRONG CU TRC

PIPELINE

Control hazard: - L xung t xy ra khi c lnh r nhnh. - Khi mt lnh r nhnh c thc thi th cha bit c a ch lnh tip theo .

2. CCH X L HAZARD
a. Structural hazard: - Thm cc thanh ghi gia cc tin trnh cha d liu c x l t cc tin trnh trc. - Cc thanh ghi s chia phn cng thnh nhng phn tng ng vi cc Stage.

2. CCH X L HAZARD
b. Data hazard: C 2 k thut x l data hazard: - Forwarding - Stalling

CCH X L HAZARD - FORWARDING

K thut forwarding: - L k thut chuyn tip d liu u ra sau khi tnh ton t b ALU hoc sau khi truy cp DataMem vo s dng lnh sau , khng ch cho n khi ghi vo RegFile.

IU KIN XY RA FORWARDING

EX hazard: If (EX/MEM.RegWrite=1) and (EX/MEM.RegisterRd!=0) and (EX/MEM.RegisterRd=ID/EX.RegisterRs)) => ForwardA=10 If (EX/MEM.RegWrite=1) and (EX/MEM.RegisterRd!=0) and (EX/MEM.RegisterRd=ID/EX.RegisterRt)) => ForwardB=10

IU KIN XY RA FORWARDING

MEM hazard: If (MEM/WB.RegWrite=1) and (MEM/WB.RegisterRd!=0) and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) => ForwardA=01 If (MEM/WB.RegWrite=1) and (MEM/WB.RegisterRd!=0) and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) => ForwardB=01

KHI FORWARDING CC TN HIU IU KHIN CHN TON HNG CHO ALU

2. CCH X L HAZARD -STALLING

K thut stalling : - L k thut tr hon vic thc thi 1 lnh ch d liu c c t cc cu lnh trc, s dng cho cu lnh sau.

IU KIN XY RA STALLING:

ID/EX.MemRead=1 ID/EX.RegisterRt=IF/ID.RegisterRs
or

ID/EX.RegisterRt=IF/ID.RegisterRt

2. CCH X L HAZARD
Control hazard: - Thc thi cc lnh bnh thng. Nu xy ra r nhnh th flush cc lnh va tm, gii m sau. - Xy dng 1 khi c th flush cc lnh tm v gii m cng on IF v ID. - iu kin flush: 1 trong nhng iu kin: + khi thc thi lnh Jump, JR + lnh BNE tha iu kin nhy

KHI X L CONTROL HAZARD:

Jump IF flush

ID flush

DISCARD INSTRUCTION

BneControl JRControl

Nu xy ra r nhnh (c lnh Jump, JR hoc tha iu kin lnh BNE) th s set IF_flush v ID_flush hy lnh tm v gii m.

KHI WB_FORWARD
Hazard c th xy ra Write Back Stage: - Khi ghi v c ti cng 1 thi im cng 1 a ch th d liu c ra khng m bo ng l d liu ang c ghi vo. - Khc phc: Dng 1 khi WB_Forward chuyn tip d liu ang ghi ti ngay u ra.

KHI WB_FORWARD
ReadData1 Out ReadData1 ReadData2 WriteData RegWrite WriteRegister ReadData2 Out

WB_Forward

rs
rt

KHI WB_FORWARD

Hot ng ca khi WB_Forward WB_RegWrite = 1 chuyn tip WB_WriteRegister khc $0 => WB_WriteData WB_WriteRegister = rs n ReadData1Out
WB_RegWrite = 1 WB_WriteRegister khc $0 WB_WriteRegister = rt chuyn tip => WB_WriteData n ReadData2Out

MIPS PIPELINE DATAPATH

EX_Memread IF_Flush ID_Flush Jump PC_Write IFID_Write EX_rt ID_rs ID_rt

Discard Instruction

Bnecontrol JRControl

Stall_flush

Hazard Detection Unit

IFID_flush
ID_flush Stall_flush flush

TIN HNH M PHNG TRONG MODELSIM Code:

Main:

xori xori j labelA: xori xori labelB: sub bne add sw lw slt xori jr

$s1,$0,0x0002 $s2,$0,0x0006 labelB $s1,$0,0x0002 $s2,$0,0x0002 $s3,$s2,$s1 $s1,$s2,labelA $s4,$s1,$s2 $s4,8($s3) $s5,8($s3) $s6,$s2,$s5 $s6,$s6,0x0001 $s6

M PHNG
MIPS Pipeline

Quartus

ModelSim