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Ayoush Johari Assistant Professor Department Of Electronics and Communication Engineering LNCTS. Bhopal
Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps
Hierarchical name
Interior view of a component:
components and wires that make it up.
Full adder
cin
sum
box1
box2
Component hierarchy
top
i1
xxx
i2
Hierarchical names
Typical hierarchical name:
top/i1.foo
component pin
Stick diagram
Transistor schematic
Mixed schematic
inverter
Levels of abstraction
Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics.
Circuit abstraction
Continuous voltages and time:
Digital abstraction
Discrete levels, discrete time:
Register-transfer abstraction
Abstract components, abstract data types:
0010
+
0001
+
0100
0011
Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts.
Design abstractions
English Executable program
specification
behavior
registertransfer Throughput, design time Function units, clock cycles Literals, logic depth
function
Sequential machines
Logic gates transistors rectangles
cost
logic
circuit
layout
nanoseconds
microns
Design validation
Must check at every step that errors havent been introduced-the longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of lessand more-abstract stages. Back annotation: copy performance numbers to earlier stages.
Manufacturing test
Not the same as design validation: just because the design is right doesnt mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade.
Architectural Design
Physical Design
Functional Design
Fabrication
Logic Design
Packaging
X = (AB+CD)(E+F) Y= (A(B+C) + Z + D)
Component list:
top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet
i1
xxx
i2
Netlist
Physical Design
Architectural Specification
Functional Design
Layout
Circuit Design or Logic Synthesis Fabrication
Chips
Packaging
RTL in HDL
Deadspace
Feedthrough
Feedthrough
Type 1 standard cel1 Type 2 standard cell
Semicustom ASICs
All logic cells are predesigned (defined in cell library) and some (possibly all) of the mask layers are customized Types: Standard-cell based and Gate-array-based ASICs
Trends: fewer and fewer full-custom ICs are being designed (excluding mixed analog/digital ASICs)
Standard-Cell-Based ASICs(2/5)
Characteristics
custom blocks can be embedded; ASIC designer defines only the placement of the standard cells and the interconnect in a CBIC standard cells can be placed anywhere on a silicon => all mask layers of a CBIC are customized manufacturing lead time is 8 weeks
Disadvantages
time or expense of designing or buying the standard-cell library time needed to fabricate all layers of the ASIC for each new design
Standard-Cell-Based ASICs(4/5)
Standard-cells are designed to fit horizontally together to form rows Internal construction of a cell
- 25 microns wide (lambda is 0.25) - AB: abutment box - BB: bounding box - Power supplies: VDD, GND - Each different shaded and labeled pattern represents a different layer - Connections: A1, B1, Z
Gate-Array-Based ASICs
In gate-array-based ASIC transistors are predefined on the silicon wafer Base cell the smallest element that is replicated Base array the predefined pattern of transistors Masked Gate Array (MGA): only layers which define the interconnect between transistors are defined by the designer using custom masks Designer chooses from a gate-array library predesigned and precharacterized logic cells (often called macros)
Characteristics
only interconnect is customized the interconnect uses predefined spaces between rows manufacturing lead time is between 2 days and 2 weeks
Characteristics
only some (the top few) mask layers are customized the interconnect manufacturing lead time is between 2 days and 2 weeks
Characteristics
no customized mask layers or logic cells fast design turnaround a single large block of programmable interconnect a matrix of logic macrocells that usually consists of programmable array logic followed by a flip-flop or latch
Types of PLDs
PROM: uses metal fuse that can be blown permanently) EPROM: used programmable MOS transistors whose characteristics are altering by applying a high voltage PAL Programmable Array Logic programmable AND logic array or AND plane, and fixed OR plane PLA Programmable Logic Array programmable AND plane followed by programmable OR plane
Depending on how
the PLD is programmed erasable PLD (EPLD) mask-programmed PLD
FPGA
a step above the PLD in complexity; it is usually larger and more complex than a PLD rapidly growing in importance
Characteristics
none of mask layers are customized a method for programming basic cells and the interconnect the core is regular array of programmable basic logic cells (combinational + sequential) a matrix of programmable interconnect that surrounds the basic cells programmable I/O cells around the core design turnaround is a few hours
Economics of ASICs
Goal
discuss the economics of using ASICs in a product and compare the most popular types of ASICs: an FPGA, an MGA, and a CBIC
Warning!
costs change rapidly and IC industry is notorious for keeping its costs, prices, and pricing strategy closely guarded secrets, so the numbers we will use to illustrate the different components of cost are approximate
Part cost
vary enormously: from a few dollars to several hundreds FPGAs are more expensive per gate than MGAs MGAs are more expensive per gate than CBICs
Architecture
high-level design of component state defined logic partitioned into major blocks
gates, flip-flops, and the connections between them
Synthesis
Verification
Logic
RTL
Circuit
transistor circuits to realize logic elements behavior of individual circuit elements
Device
Layout
geometry used to define and connect circuit elements steps used to define circuit elements
Routing
GDSII
Process
Manufacturing
Orthogonize concerns
Abstraction vs. implementation Logic vs. timing
Synthesis
Verification
RTL
Signal Integrity
Reliability
Tighter Integration
Design closure
Routing
GDSII
Manufacturing
Logic synthesis
DesignCompiler, BuildGates, Verification of synthesis
Formal Verification (Verplex) Static timing analysis (PrimeTime)
Synthesis
Verification
RTL
Routing
DFM
GDSII
Manufacturing
FPGA
Special
Analog (custom layout, I/Os and sense amps) Mixed-Signal / RF (unique to each process, no scaling)
System-on-Chip ( System-in-Package)
Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc. Define implementation platform, hardware-software co-design Performance vs. complexity
Traditional Taxonomy
Behavioral Level Design Logic Design and Simulation Logic Synthesis IO Pad Placement
Front End
Global Placement
Detail Placement Simulation Floorplanning Clock Tree Synthesis and Routing Design Verification Timing Verification Global Routing Test Generation LVS DRC ERC Extraction and Delay Calc. Timing Verification
Back End
Detail Routing
Physical design
Logic design
Specification to RTL RTL simulation
Hierarchical floorplanning
Synthesis Formal verification Gate level simulation Static timing analysis
Physical floorplanning Place and route RC extraction Formal verification Physical verification Release to manufacturing
Design for test Engineering change order
Architecture Design
Platform-based SoC Design
Platform is a library of design resources Helps design space exploration Meet in the middle
Application space
Application instance
Embedded system
Platform specification
Hardware-software co-design
System platform
Resource allocation
Selection of the types of hardware components and the number for each type to be included in the final implementation
Module binding
Assignment of operation to the allocated hardware components
Controller synthesis
Design of control style and clocking scheme
Compilation
of the input specification language to the internal representation
Parallelism extraction
usually via data flow analysis techniques
Rules of thumb for cell density are used to initially calculate design size
Logic Synthesis
Conversion of RTL to gate-level Netlist
Targeted to a foundry-specific library Can be performed hierarchically (block by block)
Timing-driven
Clock information Primary input arrival times, primary output required times Input driving cells, output loading False paths, multi-cycle paths
Interconnect delay may be calculated based on a wireload model which uses fanout to estimate delay Clock parameters (insertion delay, skew, jitter, etc.) are assumed to be attainable later in place and route
Formal Verification
RTL description and gate level netlist are compared to verify functional equivalence, thereby verifying the synthesis results
Formal methods Graph isomorphism Binary Decision Diagram (BDD)
Emerging technology that supplements the more traditional gate-level simulation approach FV also performed after place-and-route (if gate Netlist changes)
RTL Simulation
RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctness Test benches apply input stimulus to the design Several methods are used to verify the outputs
Self-checking test benches automatically verify output correctness and report mismatches Results can be stored in a file and compared to previous results Waveform displays can be used to interactively verify the outputs
Gate-Level Simulation
Covers both functionality and timing Correctness is only as good as the test vectors used Especially critical for non-synchronous designs, verification of false path and multi-cycle path constraints Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violations
PVT = Process, Voltage, Temperature
Timing constraints are similar to those used by logic synthesis Verifies setup and hold times at FF inputs; can also check timing from and to PIs and POs; can also check point-to-point delay values (with blocking of pins, etc.) As with gate-level simulation, both best- and worst-case analysis is performed Typically performed on full-chip (not block) basis
May require modified constraints for inter-block issues: multiple clock domains, multi-cycle paths, etc.
For compatibility with timing-driven layout flow, helps to have simple / single set of constraints
Other issues: incremental analysis,
Often bundled within the same cockpit as the place and route tool Give placement some initial clues to reduce complexity
RC(L) Extraction
Calculate resistance and capacitance (and inductance) of interconnects
Based on placement of cells Routing segments
Drive delay calculation, signal integrity analysis (crosstalk, other noise), static timing.
Physical Verification
DRC Design Rule Check
Spacing, min dimension rules. Verifies that layout and Netlist are equivalent at the transistor level. Dangling nets, floating nodes. Final merge of layout, routing and placement data for mask production.
Release to Manufacturing
Final edits to the layout are made Metal fill and metal stress relief rules are checked Manufacturing information such as scribe lanes, seal rings, mask shop data, part
numbers, logos and pin 1 identification information for assembly are also added
DRC and LVS are run to verify the correctness of the modified database Tapeout documentation is prepared prior to release of the GDSII to the foundry
Constraints
Architectural optimization (timing) Inter-group buses, bandwidth Clock, SI, test; validation
Floorplanning and custom WLM Power distribution (Internal, I/O) I/O driver, padring design Board-level timing, SI
Row definitions Placement of cells Congestion analysis Placement-based re-synthesis Noise minimization, isolation Clock distribution Full routing Scan stitching, re-ordering Full RC back-annotation Hierarchical timing, electrical and SI
Tape-out
Cost minimization
Timing
Synthesis (technology mapping) Placement, routing Logic transformation, transistor sizing Buffering, re-routing Gating (sleep transistors), variant Vdd Process optimization Dual-Vth
Performance optimization
Power
Power minimization
Variation (Vdd, thermal, process variation Sizing, net ordering, shielding (tox, BEOL)) Electromigration P/G design, placement, synthesis Hot electron effect (SEU)
Signal Integrity
Reliability
SPEC Functional HW/SW Optimization Perf. Model Functional Verification SW RTL SW Opt Synthesis + Timing Analysis + Placement Opt Performance RTL SW SW Opt Cockpit Auto-Pilot Optimize Hw/Sw Analyze Comm. Hw/Sw Data Model Repository Perf. Timing Power Noise Test Mfg. other HW/SW Opt Functional Verification SPEC Performance Testability Verification
Verification Cockpit Auto-Pilot Optimize Logic Place Wire other Analyze Timing Power Noise Test other
EQ check
Testability
EQ Check
EQ Check
MASKS Multiple design files are converged into one efficient Data Model Disk accesses are eliminated in critical methodology loops Verification of function, performance, testability and other design criteria all move to earlier, higher levels of abstraction followed by Equivalence checking Assertion-driven design optimizations Industry standard interfaces for data access and control Incremental modular tools for optimization and analysis
Implementation details
Routing congestion, e.g., horizontal effect. Timing optimization, e.g., layer assignment. Via blockage, pin accessibility, wrong way routing, etc.
constraints and assumptions passed downstream; not much goes upstream ignores concerns via guardbanding separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding)
construct by correction (tight loops)
reduced degrees of freedom, pre-emptive design techniques e.g., power distribution, layer assignment / repeater rules
Gates
Physical Prototype
Timing / routability known
Placement-acknowledgeable synthesis (PKS) Including global route Post-detailed-route (In-Place Optimization, i.e., IPO)
Floorplan / Placement
Chip-level CTS, top-level route and IPO, power analysis and grid design Block-level synthesis, placement, IPO, routing
Routing
Coarse Placement Drives Partitioning, Coarse Routing Drives Pin Assignment / Timing Opt
Full-chip prototype results in optimal pin placement
Results in narrower channels and reduced die size Reduces the routing congestion Improves the chip timing
Physical Prototype
Partitioning
Block 1
Block 2
Block 3
Timing Closure
Partition
Block-Level Optimization
References
1. Sedra, Adel S., and Kenneth Carless Smith. Microelectronic circuits. Oxford University Press, 1987. 2. Neil H.E. Weste, David Harris, Ayan Banerjee; CMOS VLSI Design, A Circuits and Systems Perspective, third edition, Pearson.
3. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits , A Design perspective Second edition.
4. Course Notes from Brown, Berkeley University, IITs and others
Thank You...