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PROJECT FINAL REVIEW BATCH MEMBERS : H.HARISH (20608106027) S.MANIMARAN (20608106050) R.NAVEEN (20608186056) G.

G.NAVEENKUMAR (20608106057) INTERNAL GUIDE : Mr. T.HEMANAND. M.E. ASSITANT PROFESSOR/E.C.E

OVERVIEW
OBJECTIVE
EXIXTING SYSTEM LIMITATION BLOCK DIAGRAM OF SEA

EXPLANATION
BLOCK DIAGRAM OF KEY GENERATION KEY GENERATION CONTENT ADDRESSABLE MEMORY BASIC OPERATIONS

OVERVIEW

CRYPTOGRAPHY ENCRYPTION BLOCK DIAGRAM OF ENCRYPTION OPERATION OF ENCRPTION DECRYPTION BLOCK DIAGRAM DECRYPTION FLOW CHART PROPOSAL SYSTEM MERITS CONCLUSION REFERENCES

OBJECTIVE
We are implementing Scalable Encryption Algorithm

(SEA) using Content Addressable Memory (CAM) in FPGA using Verilog-HDL coding. Scalable Encryption Algorithm Uses the Address of the data for encryption and decryption rather than using the data content directly.

EXISTING SYSTEM LIMITATION


In existing system, we have to process whole

binary data bits for encryption & decryption.


Lower data throughput. Expensive. High power consumable.

BLOCK DIAGRAM OF SEA


KeyReg[47:0] DataI[47:0] DataLd Key0[47:0] Mod KeyI[47:0] SBox BR KeyLd Clk Rst KeyReg0[47:0] KeyReg1[47:0] WR XOR Round Reg Clk Rst Ena E/DOvr DataO[47:0] DataRd Mod IWR KeyReg8[47:0] KeyReg9[47:0] Key9[47:0] Clk Rst SBox XOR BR Round Reg SMC Key9[47:0] Clk Rst WR Encryption Computational Block Mod SBox XOR Cipher data Register BR Round Reg

Plain text data Register Decryption Computational Block

EXPLANATION
The Block Diagram of scalable Encryption Algorithm

consists of four main blocks. They are


Key

Generation Block Block Block

Encryption Decryption

Connector Block

CONTENT ADDRESSABLE MEMORY


CAM compares input search data against a table of

stored data, and returns the address of the matching data. A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. The main difference of CAM from RAM =>CAM uses the address of the data where as RAM uses the data content directly.

SCHEMATIC OF MODEL CAM

SCHEMATIC EXPLANATION
A CAM search operation begins with loading the search-

data word into the search-data registers.


precharging all match lines high, putting them all

temporarily in the match state.


Next, the search line drivers broadcast the search word

onto the differential search lines.


CAM core cell compares its stored bit against the bit on its

corresponding search lines.

SCHEMATIC OF MODEL CAM


There is a match line corresponding to each word (ML0.ML1

,etc.) feeding into match line sense ampliers (MLSAs).


There is a differential search line pair corresponding to each bit

of the search word .


The MLSA then detects whether its match line has a matching

condition or miss condition.


Finally, the encoder maps the match line of the matching

location to its encoded address.

CAM CELLS
A CAM cell serves two basic functions:
Bit storage (as in RAM) and Bit comparison (unique to CAM). NOR CELL. NAND CELL.

SCHEMATIC OF NOR CELL AND NAND CELL

NOR CELL AND NAND CELL


The NOR cell implements the comparison between the

complementary stored bit D and the complementary search data on the complementary search line, SL using

four comparison transistors.


The NAND cell implements the comparison between the

stored bit D, and corresponding search data on the corresponding search lines (SL ), using the three comparison transistors

BLOCK DIAGRAM OF KEY GENERATION

KEY GENERATION
Key generation is the process of generating keys for

cryptography. A key is used to encrypt and decrypt whatever data is being encrypted/decrypted.
Modern cryptographic systems include symmetric key

algorithms and public-key algorithms.


key lengths of 128 bits (for symmetric key algorithms)

and 1024 bits (for public-key algorithms) are common.

SUBSTITUTION BOX (S-BOX)


SEA n, b uses the following 3-bit substitution table.
ST = {0, 5, 6, 7, 4, 3, 1, 2} in C-like notation. For efficiency purposes, it is applied bitwise to any set of

three words of data using the certain recursive definition.

BIT ROTATION(r)
The bit rotation is defined on nb-word vectors.
temp_reg <= data_in;

temp_reg2 <= { temp_reg[22:16], temp_reg[23],

temp_reg[15:8], temp_reg[0], temp_reg[7:1] };


data_out <= temp_reg2;

WORD ROTATION (R)


The word rotation is defined on nb-word vectors
temp_reg1 <= data_in; temp_reg2 <= { temp_reg1[15:8], temp_reg1[7:0],

temp_reg1[23:16] };
data out <=temp_reg2

CRYPTOGRAPHY
Cryptography is the art and science of secret

writing.
The term is derived from the Greek language Krytos - secret Graphos - writing

ENCRYPTION
Encryption is the actual process of applying

cryptography. The two main areas of cryptography are Cipher and Code. Cryptographic algorithms all perform the same basic function. They take two inputs a message and a key -- and transform them into a single output.

BLOCK DIAGRAM OF ENCRYPTION

OPERATION OF ENCRPTION

DECRYPTION
The process of decoding the data that has been

encrypted into a secret format. Decryption requires a secret key or password.

BLOCK DIAGRAM OF DECRYPTION

FLOW CHART OF KEY GENERATION

FLOW CHART OF ENCRYPTION

FLOW CHART OF DECRYPTION

FPGA KIT

PROPOSAL SYSTEM MERITS


CAM process only the address of binary data for

encryption & decryption.


High data-rate. In-expensive. Low power consumable.

ADVANTAGE AND FUTURE SCOPE


This is a low-cost encryption routine basically designed

for processors with a limited instruction set.


In wireless communication and mobile computing and

networking systems.
For the encryption of JPEG2000 images. In scalable video coding .In sensor networks and RFIDs.

CONCLUSION
Our paper presented FPGA implementations of a scalable

encryption algorithm using Content Addressable memory.


Simulation Results of key generation, Encryption, Decryption

are verified by model simulator.


Synthesis reports are verified by Quartus II.

REFERENCES
Andrew S. Tannenbaum , (2002) Computer Networks, Fourth Edition".
Douglas A.Pucknell , Kamran Eshraghian,(1994) Basic VLSI design, Third

Edition.
F.-X. Standaert, G. Piret, N. Gershenfeld, and J.-J. Quisquater, (2006)

SEA:A Scalable Encryption Algorithm for Small Embedded Applications,in the Proceedings of CARDIS 2006
William Stalling , (2007)Data and Computer Communications, second

Edition.

THANK YOU

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