Digital-to-Analog Analog-to-Digital

Interface Part IV Microprocessor

Data Handling Systems

Both data about the physical world and control signals sent to interact with the physical world are typically "analog" or continuously varying quantities. In order to use the power of digital electronics, one must convert from analog to digital form on the e perimental measurement end and convert from digital to analog form on the control or output end of a laboratory system.

Data Collection and Control

!eorgia "tate #niversity, $epartment of Physics and %stronomy, http&''hyperphysics.phy(astr.gsu.edu'hbase'hph.html

Digital-to-Analog Conversion [DAC]

Digital-to-Analog Conversion
)hen data is in binary form, the *+s and ,+s may be of several forms such as the --. form where the logic /ero may be a value up to *.0 volts and the , may be a voltage from 1 to 2 volts. -he data can be converted to clean digital form using gates which are designed to be on or off depending on the value of the incoming signal.

Digital-to-Analog Conversion
$ata in clean binary digital form can be converted to an analog form by using a summing amplifier. 3or e ample, a simple 4(bit $'% converter can be made with a four(input summing amplifier.

Digital-to-Analog Conversion
1 Basic %pproaches
)eighted "umming %mplifier 5(15 6etwor7 %pproach

Weighted Sum DAC

8ne way to achieve $'% conversion is to use a summing amplifier. -his approach is not satisfactory for a large number of bits because it requires too much precision in the summing resistors. -his problem is overcome in the 5(15 networ7 $%9.

Weighted Sum DAC

R-2R Ladder DAC

R-2R Ladder DAC

R-2R Ladder DAC

-he summing amplifier with the 5(15 ladder of resistances shown produces the output where the $+s ta7e the value * or ,. -he digital inputs could be --. voltages which close the switches on a logical , and leave it grounded for a logical *. -his is illustrated for 4 bits, but can be e tended to any number with :ust the resistance values 5 and 15.

DAC0 !0"DAC0 !2 -#it $% Com&ati'le DAC

%n advanced 9M8"'"i(9r 0(bit multiplying $%9 designed to interface directly with the 0*0*, 0*40, 0*02, ;0*<, and other popular microprocessors. % deposited silicon(chromium 5(15 resistor ladder networ7 divides the reference current and provides the circuit with e cellent temperature trac7ing characteristics =*.*2> of 3ull "cale 5ange ma imum linearity error over temperature?.

(y&ical A&&lication

Analog to Digital Conversion [ADC]

ADC #asic %rinci&le

-he basic principle of operation is to use the comparator principle to determine whether or not to turn on a particular bit of the binary number output. It is typical for an %$9 to use a digital(to( analog converter =$%9? to determine one of the inputs to the comparator.

ADC )arious A&&roaches

@ Basic -ypes $igital(5amp %$9 "uccessive %ppro imation %$9 3lash %$9

Digital-Ram& ADC
9onversion from analog to digital form inherently involves comparator action where the value of the analog voltage at some point in time is compared with some standard. % common way to do that is to apply the analog voltage to one terminal of a comparator and trigger a binary counter which drives a $%9.

Digital-Ram& ADC

Digital-Ram& ADC
-he output of the $%9 is applied to the other terminal of the comparator. "ince the output of the $%9 is increasing with the counter, it will trigger the comparator at some point when its voltage e ceeds the analog input. -he transition of the comparator stops the binary counter, which at that point holds the digital value corresponding to the analog voltage.

Successive a&&ro*imation ADC

Illustration of 4(bit "%9 with , volt step si/e

Successive a&&ro*imation ADC

Much faster than the digital ramp %$9 because it uses digital logic to converge on the value closest to the input voltage. % comparator and a $%9 are used in the process.

+lash ADC
It is the fastest type of %$9 available, but requires a comparator for each value of output. =A@ for A(bit, 122 for 0(bit, etc.? "uch %$9s are available in I9 form up to 0(bit and ,*(bit flash %$9s =,*1@ comparators? are planned. -he encoder logic e ecutes a truth table to convert the ladder of inputs to the binary number output.
Illustrated is a @(bit flash %$9 with resolution , volt

+lash ADC
-he resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is :ust the propagation delay through the networ7 ( it is not limited by the cloc7 rate or some convergence sequence.

ADC0 0*, -#it $% Com&ati'le A"D Converters

CMOS 8-bit successive approximation A/D converters that use a differential potentiometer laddersimilar to the 2 !" products# $hese converters are desi%ned to allo& operation &ith the 'SC8(( and )'S8(8(A derivative control bus &ith $")-S$A$* output latches directl+ drivin% the data bus# $hese A/Ds appear li,e memor+ locations or )/O ports to the microprocessor and no interfacin% lo%ic is needed# Differential analo% volta%e inputs allo& increasin% the common-mode re-ection and offsettin% the analo% .ero input volta%e value# )n addition/ the volta%e reference input can be ad-usted to allo& encodin% an+ smaller analo% volta%e span to the full 8 bits of resolution#

ADC0 0* +eatures
Compatible &ith 8(8( 01 derivativesno interfacin% lo%ic needed - access time - 23 ns *as+ interface to all microprocessors/ or operates 4stand alone5 Differential analo% volta%e inputs 6o%ic inputs and outputs meet both MOS and $$6 volta%e level specifications 7or,s &ith 2# 8 96M33!: volta%e reference On-chip cloc, %enerator (8 to 8 analo% input volta%e ran%e &ith sin%le 8 suppl+ 'o .ero ad-ust re;uired

ADC0 0*, inter-acing

P85-, $BV ** C49@C4 *, %'$ , *1 %'$ 1 *@ %'$ @ *4 %'$ 4 *2 %'$ 2 *A %'$ A *C %'$ C

. / A
-hatDs all for this time.