A Project Presentation on

DESIGN AND IMPLEMENTATION OF SQUARE & CUBE ALGORITHM USING VEDIC MATHEMATICS

UNDER THE GUIDANCE OF Dr. REKHA K.R. PROFESSOR, ECE Dept. 2012-2013

BY PRADEEP.S 1ST SEM (M.TECH) VLSI & EMBEDDED SYSTEM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

SJB INSTITUTE OF TECHNOLOGY

KENGERI, BANGALORE-560060

OVERVIEW
Introduction

Literature survey
Basic Concept Block diagram of square algorithm and cube algorithm Experimental result Conclusion and future scope References

INTRODUCTION
Multiplication is an important fundamental function in

arithmetic operations.
The process of raising a number to a power i.e.,

exponentiation is an important operation. The exponentiation operation, like square and cube plays a vital role in communication systems, signal processing applications..

 Squaring and cubing can be performed using ordinary

multipliers, which are scalable but they have a larger delay.

Structure based array implementation are faster but scalability

increases design complexity as well as expense. Moreover, multipliers occupy large area, have long latency and consume considerable power.
Therefore, which offer either of the following design targets-

scalability, re-configurability, high speed, low power consumption, regularity of layout and less area or even a combination of some of these features are to be designed.

LITERATURE SURVEY

There are number of techniques that to perform binary multiplication. In general, the choice is based upon factors such as latency, throughput, area, and design complexity.
Array Multiplier, Booth Multiplier and Wallace Tree Multipliers are some of the standard approaches to have hardware implementation of binary Multiplier.

Array Multiplier gives more power consumption as well as the optimum number of components required ,but delay for this Multiplier is larger .It also requires large

number of gates because of which area is increased ;due to

this array Multiplier is less economical .Thus ,it is a fast Multiplier but hardware complexity is high.

In the Wallace tree Multiplier ,the circuit layout is not easy although the speed of the operation is high

PROBLEM FORMULATION The problems that are to be handled in this present work is 1. To reduce area and delay. 2. To minimize power consumption. 3. To design a Multiplier with regular in structure. OBJECTIVE The main objective of this work is to implement an Arithmetic unit which makes use of Vedic Mathematics algorithm for multiplication. The Arithmetic unit that has been made performs multiplication, addition, subtraction and Multiply Accumulate operations. The MAC unit, used in the Arithmetic module uses a fast multiplier, built with Vedic Mathematics Algorithm. Also, square and cube algorithms of Vedic Mathematics, to reduce the multiplications required

 Reducing the time delay and power consumption are very

essential requirements for many applications.

Multiplier based on Vedic Mathematics is one of the fast and low

power multiplier.
In the present work we are using the Vedic sutras to compute the

square and cube of the input number.

To compute square we have made use of the Duplex property of

Urdhava Triyakbyam Sutra.

To find the cube of the number Anurupya Sutra of Vedic

mathematics is used.
This approach of obtaining the square and cube of a number is fast

and it is easy and simple to implement.

VEDIC SUTRAS
Vedic mathematics is mainly based on the 16 sutras

dealing with various branches of mathematics like arithmetic, algebra, geometry etc..

Urdhva Triyakbyam Sutra

Anurupya Sutra

Block diagram for square architecture

(X1X0)

X1
multiplier

X1

X0

X0
multiplier

multiplier

X12

X1*X0

X02

<<
2X1X0

Let us consider how to obtain the square of a two bit number :(X1X0) X1 X0 X1 X0 P3 P2 P1 P0

Where P0 = D(X0) = X02 P1 = D(X1 X0) = 2*X1*X0 P2 = D(X1) = X12

Implementation of cube algorithm

Block diagram for cube architecture (X1X0)

X1xxx
X1 multiplier X12 X1 X0 X1 X0 multiplier X0

multiplier

multiplier

multiplier

multiplier

X13

X12X0 << <<

X1X02

2 X12X0

+ 3X12X0 + 3X1X02

2X1X02

(X1X0)3

EXPERIMENTAL RESULT
Result of Square algorithms

Result of Cube algorithms

 CONCLUSION

It is evident from the results that implementation of Vedic square algorithm using Wallace tree multiplier is better than that of using array multiplier in terms of power and area. Also Vedic mathematics approach of obtaining square and cube is faster and the power consumption is also reduced due to parallel computation. There is an overwhelming need to explore Vedic algorithms in detail so as to verify its applicability in different domains of engineering. FUTURE WORK

Vedic Mathematics, developed about 2500 years ago, gives us a clue of symmetric computation. Vedic mathematics deals with various topics of mathematics such as basic arithmetic, geometry, trigonometry, calculus etc. All these methods are very efficient as far as manual calculations are concerned. If all those methods effectively implement hardware, it will reduce the computational speed drastically. Therefore, it could be possible to implement a complete ALU using all these methods using Vedic mathematics methods. By using these ancient Indian Vedic mathematics methods world can achieve new heights of performance and quality for the cutting edge technology devices.

REFERENCES
M.Ramalatha, K.Deena Dayalan, P.Dharani, A Novel Time And

Energy Efficient Cubing Circuit Using Vedic Mathematics For Finite Field Arithmetic.
Chandra Mohan Umapathy, High Speed Squarer.

Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, Design and

Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics.
Ramachandran.S,

Kirti.S.Pande

Design,

Implementation

and

Performance Analysis of an Integrated Vedic Multiplier Architecture.

THANK YOU