Substrate Noise Analysis and

Reduction in High Frequency IC

Design

By: Albert Onabajo

Northwestern Polytechnic University
PHD Seminar April 30th 2005
 What is noise?

Noise is a Physical process that

interferes with transmission of a Signal
or message.
 What is noise?
The main sources physical noise in
a system are: Shot, Thermal,
Burst, Avalanche and Flicker noise.

1. Physical Noise Sources

i. Thermal noise.
Sometimes called Johnson-Nyqiust Noise is the noise
generated by the equilibrium fluctuations of the electric
current inside an electrical conductor, due to the random
thermal motion of the charge carrier (the electrons).
 Thermal noise at room temperature can be
estimated in decibels as:
P = − 174 + 10log(Δf)
Where P is measured in dBm (0 dBm = 1 mW) and Δf is
bandwidth in Hz.

Noise Voltage =

Noise current =

The spectra density of thermal noise with

frequency is flat, and is known as white noise.
 What is noise?…
(ii) Shot noise – This noise is generated by current flowing across a P-
N junction and is a function of the bias current and the electron
charge.

-- The impulse of charge q is detected as a single shot event in the

time domain can be Fourier transformed into the frequency domain
as a wideband noise
 What is noise?...
(iii). Burst noise – occurs in semiconductor devices, especially
monolithic amplifiers.

(iv). Avalanche noise – occurs in Zener diodes breakdown

phenomenon. It is created when a PN junction is operated in a
reversed biased mode.

-- This noise is considerably larger than shot noise, so if zeners have to

be used as part of a bias circuit then they need to be RF decoupled.

(v). Flicker or 1/f noise – This noise occurs in MOS devices due to
interface traps.

-- Flicker noise is usually defined by the Center Frequency (fc).

 What is noise?...
2. Man-made (or environmental) noise:

i. Man-made noise can be orders of

magnitude larger than physical noise
sources.
 What is noise?...
ii. For CMOS digital circuits, noise
is any deviation in the analog
voltage from the nominal supply
or ground rails when the node
should represent a stable logic ‘0’
or ‘1’ value.
 What is noise?

In general:
-- Noise is the auditory experience of
sound that lacks musical quality

In Engineering:
-- Noise is a question of Signal Integrity,
and Cross-Talk is one of the byproducts.
 What is Signal Integrity?
-- Design with signal integrity means preservation of the
intended behavior of a circuit in the presence of noise.

-- The quality of an electrical signal or pulse on the

interconnect track of a PCBA or component.

-- Designers, particular high frequency circuit designers

have to make allowance for impedance matching, and
signal transmission effect like Noise to prevent signal
deterioration, distortion or oscillation.
 What is Substrate Noise?
Millions of gates integrated on a chip may generate
substrate potential fluctuation large enough to
impair sensitive analog circuits on the same chip.

As a result, the substrate noise coupling can

severely degrade the performance of sensitive
circuitry.
Modeling the Substrate
 What is needed for Substrate
Noise Analysis
Physical Design Information (GDSII)

Layout Extracted Netlist (SPICE) / Cell-Based P&R Data

(DEF)

Dynamic switching information (Spectre, PowerMill output)

or Static /Dynamic switching information (VCD)

Substrate current library view

Package Netlist (SPICE)

-- Substrate Noise Analysis should incorporated into the design flow as early as
during the floor planning to ensure that talkers and listeners are placed to minimize
cross-talk and noise injection
 What we need for crosstalk
analysis?
Extracted coupled distributed interconnect
parasitics
Static timing information
-- Static logic constraints
-- Timing windows
-- Slews (slews and the Timing window of the
aggressors are most critical Noise-on-Delay)
Noise library view
Substrate Noise Injection mechanisms

A digital switching device induces

currents to the substrate through the
depletion capacitances of the device p-n
junctions.

The output buffers may be particularly

noisy, as well as common-emitter
bipolar transistors.
Substrate Noise Injection mechanisms
Due to the inductances associated to package pins:

noise at the power-supply lines (delta-i noise) is usually large in

CMOS circuits.

These supply lines are typically used to bias the wells and substrate
in the digital section. Thus the amount of noise introduced to the
silicon bulk may be very large, all depending on the number and
location of contacts and the delta-I noise level.

Also, this noise may forward-bias protection diodes, and introduce

substrate currents.
Substrate Noise Injection mechanisms

Also, interconnect capacitances add to the

junction capacitances. A particular case of this
interaction is the noise coupled from spiral
inductors in RF IC’s.

• Accurate analysis requires extraction of wells, contacts, well taps

• For additional accuracy interconnect extraction can also be considered
Substrate Noise Injection mechanisms

As device feature sizes are being reduced:

impact-ionization currents have gained

significance.

although traditionally the noise capacitively

coupled through the junction is larger than
impact-ionization, in deep submicron devices
hot-carrier effects become a major source of
noise injection
Sources of Substrate Noise
 Sources of Substrate Noise
Injection of substrate noise:
Typical active devices include bipolar junction transistors, MOS
transistors and diodes. Typical passive device include resistor,
capacitors, inductors, and interconnects. Local wells and diffusions are
bellowed to passive structures.

Reception of substrate noise

The reception of noise by most devices on the surface takes place
through capacitive sensing. This is true of bipolar transistors, capacitors,
resistors, and interconnect lines.

Transmission of substrate noise

Substrates act as the media for coupling of noise from one device to
another
 The Origin of Substrate Noise

A mixed-signal IC circuit is a very noisy place:

–Analog always vulnerable

The delta-i or switching noise at the power supply lines is a

contributor to substrate noise.

Typical active devices include bipolar junction transistors,

MOS transistors and diodes.
 Noise Origin…
-- Logic signals switching from Gnd (0)->Vdd (1), and/or Vdd

(1) ->Gnd (0) couple to other quiet or switching nets

through unintended “couplings”
 Substrate Noise Origin…..
Currents from Device junctions and channels
– Supply currents injected into the substrate through the
substrate contacts
 Noise Sensitivity Analysis
• Noise Analysis: Noise current injected
Y.v=I into the substrate

Noise Sensitivity Analysis:

•Admittance Substrate node voltage
Matrix
Y . dv/dp = di/dp –d Y/dp .v

Sensitivities of voltages, currents and admittances

to parameter, p
 Substrate Noise Reception
Mechanisms
Noise present in the substrate may interact with
MOS transistors in two ways:

1). through the junction capacitances and through body-

effect.

2). Analog sections may have the substrate biased with the
analog power-supply lines. If so, substrate noise may be
acquired by these lines through the contacts, and thus
affect the analog circuitry.
 Noise reception mechanisms..
Noise attenuation behavior depends on the type of wafer.

-- lightly-doped wafers are about less noisy than heavily-doped epi ones,

-- the presence of a grounded backside contact has negligible influence even in

a heavily-doped wafer

- A typical two-transistor amplifier analog sensor configuration

 Why are noise problems getting
worse?
Interconnect scaling

– More levels of interconnect, aggressors and victims, are

packed closer together.

– Metal thickness remains constant because of resistance

– In scaling from 1.8 um to 0.9 um pitch, line-to-line

capacitance increases from 46% to 68% of full-loaded
self-capacitance.
• Faster clock frequencies and slew times
• Higher current density demands
 Mitigating Substrate Noise
Noise increases with increase in
frequency,

Noise isolation typically degrades at

higher frequencies
Mitigating Substrate noise in sensitive Analog cells
(e.g. Op-Amp)

Splitting power will reduce substrate noise

-- Additional pins is required but with no additional space

 Mitigating Substrate noise in sensitive
Analog cells (e.g. Op-Amp)
Backside Grounding has little effect on substrate noise reduction for high frequency ic.

-- A backside connection through a 5nH wire bond may only improve isolation at
a PLL ring by about 0.03dB
 Mitigating Substrate noise in sensitive
Analog cells (e.g. Op-Amp)…
Extending the N-Well under the compensation
devices may improve noise immunity by upto
50%

A sensitive Analog cell

(An Op-Amp)

Goal: locate the most sensitive parts of the analog cell and
improve the noise immunity (lightly doped substrate)
 Mitigating Substrate noise in sensitive
Analog cells (Non Inv. Op-Amp)…
P+ ring around the cells may increase noise immunity by about 80%

p+ ring
 Mitigation of Substrate Noise…
Use Nwell
-- to isolates resistors from substrate.
-- to isolated bottom plate from substrate.
-- Nwell rings and p diffusion substrate contacts to reduce
noise.

Add diffusion ring around segmented Nwell.

Add multiple rows of contacts.

Mitigation of Substrate Noise…
the substrate thickness and doping concentrations – Lightly doped
substrate has more noise immunity.

the physical separation between noise aggressors and victims

the placement of substrate contacts, guard rings, and wells

the use of a backplane substrate contacts/biasing

signals transition times

routing of the power lines.

Splitting power reduces substrate noise

 Substrate Noise Measurements

With the high level of complexity and

integration, substrate noise has become
an important consideration in the design.

Thus a simple and accurate substrate

measurement is required for the analysis
of system on a chip.
 Challenges
It is very difficult to isolate and measure the
substrate coupling in real circuits.

Noise through packages and boards couples

sections of circuit are very strongly as well.
This is especially the case at high
frequencies.
 A Measurement approach…
It uses down-conversion to isolate the noise coupled
through the substrate

a VOC is used as a noise generator.

an external signal is supplied to the chip as a

frequency that is slightly offset from the VCO’s
frequency.

In effect an heterodyne down-converter is implemented

on-chip to isolate substrate noise.
Heterodyne Down-Conversion
 Substrate Noise Coupling Model

Noise Coupling

Guard Rings can increase noise at the Analog circuit if:

(1). Zs < Zpd
(2). the Guard Ring is tied to a noisy supply,. it will inject substrate
noise.
 Conclusion
Substrate noise is created mostly from high
frequency mixed-signal integrated circuit. The
noise coupling from the substrate can severely
degrade performance of noise sensitive circuits.

Therefore substrate noise reduction and analysis

must included in the early part of the design flow
of high frequency ic circuits.
 References
H. Chen and D. Ling, “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design,” Proceedings
of the 37th Design Automation Conference, pp. 638-642, June, 1997.

Xavier Aragon`es and Antonio Rubio, “Experimental Comparison of Substrate Noise Coupling Using Different Wafer
Types” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999, pp. 1405 – 1409.

K. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design,” Proceedings of the IEEE International
Conference on Computer-Aided Design, 1996, pp. 524-531.

Nishath Verghese, “CAD Tools for Signal Integrity Analysis of Mixed-Signal ICs,” Cadence Design Systems, 2OOO

Albert Onabajo, “Performance Driven Power Grid Analysis and Noise in Very High Speed VLSI, SoC, and ASIC ic
Design”, Department of Electrical and Computer Engineering, University of Texas, Dallas, TX. 2003.

Philippe Duchene, “Substrate Noise Analysis and Simulation with SubstrateStorm”, 2001 Simplex Solutions, Inc. 2001

J. P. Costa, etc. “Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal Ics”,
IEEE Trans. On Computer-aided design, pp. 597-607, May 1999

A. Samavedam, etc. “A scalable substrate noise coupling model for design of mixedsignal
IC’s” IEEE Journal of Solid-state Cirucits, Vol. 35, No.6, pp 895-904, June 2000
HAVE A NICE
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