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Commercial-Density SRAMs:
A Comprehensive SEE and TID Study
Jeff Draper, Y. Boulghassoul, M. Bajura, R. Naseer, J. Sondeen and S. Stansberry
University of Southern California
Information Sciences Institute
This work was supported by the Defense Advanced Research Projects Agency (DARPA)
Microsystems Technology Office under award No. N66001-04-1-8914
Any opinions, findings, and conclusions or recommendations expressed in this presentation are those of the authors
and do not necessarily reflect the views of DARPA/MTO or the U.S. Government
Motivations
• Latchup response
3
Overview SRAM Test Chips
DESIGN COMMERCIAL “AS MODIFIED FOR SPACE
ATTRIBUTE IS” - BASELINE OPERATIONS –
HARDENED
IBM PROCESS 9LP
Size (Total Bits) 65, 536 90, 112
Voltage (V) Core: 1.2 V; I/O; 2.5 Core: 1.2 V; I/O; 2.5
I/O Pads Radiation-Hardened Radiation-Hardened
Design Libraries: Phase-1 (RHBD) Phase-1 (RHBD)
Error Correction None 1 bit (Hamming; 22, 16, 4)
Area Overhead 1X 1.37X
IBM PROCESS 9SF
Size (Total Bits) 57,344 122,880
Voltage (V) Core: 1.0 V; I/O; 2.5 Core: 1.0 V; I/O; 2.5
I/O Pads Commercial (Artisan) Commercial (Artisan)
Design Libraries: Commercial (Artisan) Commercial (Artisan)
Error Correction None 2 bits (BCH; 15,7,5)
Area Overhead 1X 2.14X
0 1 2 3 0 1 2 3 0 1 2 3
Voter
0 1 2 3 0 1 2 3 0 1 2 3
0 1 2 3 0 1 2 3 0 1 2 3
0 0 0 1 1 1 2 2 2 3 3 3
0 0 0 1 1 1 2 2 2 3 3 3
TMR 0 0 0 1 1 1 2 2 2 3 3 3
Annular gates
(TID)
Guard rings 5
(SEL)
- Single Event Effects -
SEU
6
SEU Raw Cross Sections
HI Test Results
BASELINE
LP SF
HARDENED
LP SF
Memory Patterns={00,11,10}, Static/Dynamic = {s, d}; LP Dynamic Access Rate 2.2 KHz per bit; SF Dynamic Access Rate 718 Hz
Data collected at LBNL 88” Cyclotron, 10 MeV cocktail, core voltage 10% below nominal, 100 MHz tester. Fluence range 1e7-1e5. #Errors>256 ea. pt.
7
SEU Cross Section Calculations
Pre-ECC and Scrubbing
s
• Weibull(x) = [ a ]*[ 1-e{ ((x-x0)/w)) } ]
• SF cross-section ~ 2-3 X higher than
LP, likely due to lower Vdd
• No cross-section dependence on
static vs. dynamic testing
• Minor differences between baseline
and hardened suggest little impact of
TMR control circuitry
8
SEU Model
ECC and Scrubbing *
P(error) per scrub vs. ECC and Scrub Rate BER reduction vs. ECC and Scrub Rate
2
1
• Distribution of observed errors from measurements matches the ECC model very
well
Proper error correction code (ECC) and modest scrubbing rate combination
ensures a BER better than 10-10 errors/bit-day in all orbital scenarios 10
SBU and MBU analysis vs.
Effective LET
Single and Multi Bit Upset Distributions vs. Effective LET for LP and SF SRAMs
9LP
9SF
• IBM 90nm commercial density SRAM cells have a very low upset threshold
From 3D TCAD simulations, worst-case Qcrit ~1.1fC
• With an SRAM cell threshold LET < 0.5 MeV.cm2/mg, protons could
potentially become capable of inducing SEUs through direct ionization
Possible drastic increase in raw memory cell BER
Could flood 1bit and possibly even 2 bit ECC schemes
12
- Single Event Effects -
Latchup
13
Latchup in 90nm SRAMs
Device
Experimental
LP BASELINE LP HARDENED SF BASELINE SF HARDENED
Condition
9LP and 9SF SRAM Core leakage currents dynamics as a function of TID and 24C anneal
1.E-06 1.E-06
Leakage Current / Bit (A)
1.E-08 1.E-08
1.E-10 1.E-10
0 500 1000 1500 2000 1 10 100 1000
Cummulated Dose (krads) Annealing Time @ 24C (days)
9LP and 9SF SRAM IO leakage currents dynamics as a function of TID and 24C anneal
1.E-01
1.E-01
1.E-02
Leakage Current (A)
1.E-02
1.E-04 1.E-04
1.E-06
1.E-06
1 10 100 1000
0 500 1000 1500 2000
Annealing Time @ 24C (days)
Cummulated Dose (krads)
All devices irradiated @ 200 rads/sec, Max Temp < 30 C, removed ~15 minutes for measurement
LP irradiated under 10 pattern & measured under 01; SF irradiated under 00 pattern & measured under 11 17
9LP/9SF TID Responses for
100C and 150C anneals
• All 9LP and 9SF SRAMs respond very well to a temperature annealing
For 100C, Core leakage currents are within 3X of pre-rad < 100 hours
For 150C, pre-rad Core leakage levels are reached within 5 hours
9LP and 9SF SRAM Core leakage current variation as a function of annealing temperature
1.E-06 1.E-06
Leakage Current / Bit (A)
1.E-08 1.E-08
1.E-09 1.E-09
1.E-10 1.E-10
0 50 100 150 0 20 40 60 80 100
Annealing Time (hours) Annealing Time (hours)
18
TID Radiation Hysteresis
1.E-06 1.E-06
1.E-07 1.E-07
1.E-08
1.E-08
9LP Core @ 1.2V
9LP Core after 58h@180C 9SF Core @ 1V
1.E-09
1.E-09 9SF Core after 58h@180C
9LP 2nd TID exposure
9SF 2nd TID exposure
1.E-10
1.E-10 0 500 1000 1500 2000
0 500 1000 1500 2000
Cummulated Dose (krads)
Cummulated Dose (krads)