SRAM Leakage Suppression by

Minimizing Standby Supply Voltage

Huifang Qin, Yu (Kevin) Cao, Dejan Markovic,

Andrei Vladimirescu, and Jan Rabaey

Berkeley Wireless Research Center,

University of California, Berkeley
Outline
 Motivations
– SRAM leakage suppression for ultra-low power applications
– Exploring Ultra-Low Voltage (ULV) SRAM operation capability

 Modeling
– The SRAM Data Retention Voltage (DRV)

 Design and Implementation

– Dual-rail leakage suppression scheme with ultra-low standby Vdd

 Measurement Results and Analysis

– To Minimize the SRAM DRV

 Conclusion and Future Work

ISQED 2004 H. Qin -2-
Motivation I: Leakage Suppression of Embedded SRAM

 Nowadays the embedded SRAM circuits in a

microprocessor system typically consumes:
– 90% of the total processor transistor count
– 60% of the chip area
– 20% ~ 50% of chip power
– 100% of ULP system leakage power?

 Power-efficient design is critical for portable electronics

– To extend battery life requires maximum power savings. Even more
demanding is to enable energy scavenging

Target application:
Ultra-Low Power (ULP) wireless sensor network

ISQED 2004 H. Qin -3-

Motivation I: Leakage Suppression of Embedded SRAM

 The situation is further exaggerated by scaling

– 7.5X leakage increase for each technology generation
– The ever-increasing process variations make things even worse.
Leakage
(A) 0.13um Technology

 Embedded memory
leakage suppression is
both crucial and effective
for deep sub-micron ultra
low power, low duty cycle 0.18um Technology

system design.
Vdd (V)

Leakage of 1K byte SRAM Module

ISQED 2004 H. Qin -4-

Motivation II: Exploring Low Voltage SRAM Operation

• Technology driven

• Effectively reduces

design power
consumption

Vdd scaling: most effective approach in achieving

ultra-low power design. Question: What is
the SRAM capability
for ULV operation?

(Figure courtesy of Intel)

ISQED 2004 H. Qin -5-
The Simple Scheme: SRAM in Ultra-Low Vdd Standby

(1V)

(?)

Goal of the Scheme

• Minimize standby leakage power
• Robust preservation of memory content

 More to find out

– What is the Data Retention Voltage (DRV) of SRAM?
– How to model DRV from process parameters?
– Any effective way to do DRV-optimized design?

ISQED 2004 H. Qin -6-

Look Around: Existing Approaches for Low Leakage SRAM

 Circuit level:
– Dynamic control of Gate-Source and Substrate-Source Vbias
• Large design and area overhead
• Limited saving on leakage power

 Micro-architectural level:
– Vdd gating off for idle memory sections
• Ineffective for caches with large utilization ratio
– Drowsy cache: put inactive cache lines in a low voltage
standby mode
• Achieves over 70% leakage energy saving in a data cache
• Question to be answered: how deep a snap can it be?

ISQED 2004 H. Qin -7-

Look Around: What is Unique in This Work

 A thorough study of ULV SRAM data

retention behavior

 An effective leakage suppression

standby scheme for ULP applications
– The whole SRAM is put in standby mode
– Maximum leakage saving and minimum design
overhead

ISQED 2004 H. Qin -8-

The Data-Retention Voltage (DRV) of SRAM

VDD
0 DRV Condition:
0
M1 M3
M5
V1
V2 ∂V1 ∂V1
VDD M6 VDD = , when VDD = DRV
∂V2 Left inverter
∂V2 Right inverter
M2 M4
Leakage Leakage
current current

VTC of SRAMcell inverters

0.4

 When Vdd scales down to DRV, 0.3

V
DD
=0.4V

the Voltage Transfer Curves

(VTC) of the internal inverters

)VV(2(V)
0.2 V =0.18V
degrade to such a level that
DD

2
V
Static Noise Margin (SNM) of 0.1 VTC
1
the SRAM cell reduces to zero. VTC
2

0
0 0.1 0.2 0.3 0.4
V (V)
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Modeling SRAM DRV

DRV analytical model:

∆Si
∆DRV = DRV 0 + ∑a i
i Si
+ ∑b∆ V
i
i + c∆ T
thi

where DRV0 is the nominal value at 27ºC

• Coefficients extracted from transistor

characterizations, such as Vthi , ni, I0i .

• Model can be used for DRV-aware

SRAM design optimizations
Modeled and simulated DRV as a
function of transistor width scaling.
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Design of Dual-Rail SRAM Standby Scheme

Designed for ULP system:

5:1  Standby Vdd noise margin:
VDD SC VDDstandby – 100mV Guard band over DRV
Conv
gives 55mV W.C. SNM
 Delay overhead
Stby – A 200μm wide PMOS power
switch wakes up the memory in
within 10ns
4k Bytes  Wake up power overhead:
SRAM
– Minimum standby time for positive
power saving estimated to be
around tens of μs.

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Switch Capacitor (SC) Converter Design
(a) SC Conv design C lk Clk

10 pF 10 pF 10 pF 10 pF 10 pF
0.66 0.66 0.50 0.50 0.50

0.24 0.35 0.24 0.35 0.24 0.35 0.24 0.35

Clk
 Compared to magnetic-
based voltage regulators
Rmem (numbers indicate transistor w idth in microns)

(b) Operation phases

C Clk
– Higher efficiency
Clk C – Smaller current ripple
Equalizing phase
1V C Charging phase – Easier on-chip integration
C
C C C C C Rmem C Rmem

 Optimized SC converter design achieves 85% power

efficiency with 1V input and estimated output load

ISQED 2004 H. Qin - 12 -

4KB SRAM Leakage Control Scheme Test Chip
1.4 mm

IP
Module
1.4 mm of 4kB
SRAM

Standby supply voltage

Test chip in 0.13um technology regulator design

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SRAM DRV Measurement

SRAM DRV test suite

Waveform of DRV measurement

(a) DRV = 190mV in SRAM cell 1 with state “1”
(b) DRV = 180mV in SRAM cell 2 with state “0”
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SRAM Measurement Results
6000
60
Histogram of 32K SRAM cells

50

4000 40
Leakage Current (μA)
30 Measured
DRV range
20
2000
10

0
0 0.2 0.4 0.6 0.8 1
0 Supply Voltage (V)
50 150 250 350 450
DRV (mV)
• More than 90% reduction in
• Measured DRV: 80mV ~ 250mV leakage power with 350mV
(0.13 µ m CMOS, 300mV Vth ) standby Vdd (100mV guard band).

 Storage requirement sets Vdd lower limit at 250mV without error

tolerant design
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Analysis: What affects SRAM DRV

 Process variation
(ΔL, ΔVth )
 Chip temperature
 SRAM cell sizing

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Resize SRAM Cell: for Optimum DRV
VDD
0
0
M1 M3
VDD M5
V1
V2  Current sizing
M6 VDD
– Performance optimized
M2 M4
Leakage
current
Leakage
current
– Provides poor DRV

 To optimize for DRV

– Change P/N ratio
– Smaller NMOS
– Larger PMOS

DRV vs. Transistor size Tuning

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DRV-Aware SRAM Cell Sizing Optimization (NMOS)

 Area vs. Performance: already

 By sizing NMOS (W/L) smaller,
best traded off
DRV mean value can be
reduced by 20~30mV.  Leakage power vs. Performance:
best at 20% higher delay.
 (30% delay increase = 50% leakage power reduction)
ISQED 2004 H. Qin - 18 -
Conclusions and Current Work

 SRAM DRV modeled and silicon-verified

– DRV from 80mV to 250mV for 0.13μm technology, 300mV Vth .
– DRV model facilitates optimization for ULP SRAM design

 Dual-rail standby scheme saves over 90% Pleakage

– Effective and low-cost approach for ULP applications

 DRV can be minimized by:

– Effective control on process variations (***)
– Avoid high temperature operation (*)
– SRAM cell sizing optimization at tradeoffs with speed and area (**)

 Can we further bring down the SRAM Vdd ?

– A fix at the architecture level may be more effective – use error correction
schemes to tolerate ULV errors

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