Statistically-Aware SRAM Memory Array

Design
Evelyn Grossara, Michele Stucchi,
Karen Maexa and Wim Dehaenea

IMEC , Leuven, Belgium

a
Also at Department of Electrical Engineering (ESAT) ,
Katholieke Universiteit Leuven, Belgium
grossar@imec.be

ISQED 2006
San Jose, CA, USA

© imec 2006
 Outline

Introduction
Statistically-Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 2

 Introduction

Parametric variations Device performance

affect device performance variations affect yield
[Asenov, ESSCIRC’04]
S High frequency
variations in G High standby
the number
D leakage current
and position Low frequency
of dopants Low standby
leakage current

Icrit
Distributions of frequency
and standby leakage current
Id,sub Vth (Isb) in microprocessors
(0.18um)
significant parameter variations
[Borkar, DAC’04]
(Vth, Id,sub) from device to device

© imec 2006 Evelyn Grossar-TAD- 3

 Outline

Introduction
Statistically-Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 4

 Statistically-Aware Optimization

Statistically-Aware optimization of circuits

= use statistical information on the variation of
transistor parameters during circuit optimization in
terms of speed, energy and yield

For the SRAM cell:

- explore trade-offs for optimized leakage power versus
1. delay constraint:
Vdd

BLB wl
Vdd
PUP1 PUP2
wl
Vdd
BL
Read current of weakest
1 0 SRAM cell mainly limits the
PG1 VL VR PG2 delay constraint
PDN1 PDN2 (first order approximation)

gnd

2. functionality constraints (read stability and write-ability)

© imec 2006 Evelyn Grossar-TAD- 5
 Performance parameters of SRAM cell:
Read stability and write-ability
Read Stability Write-ability
Vdd

VBLdd->0V
SRAM cell is most vulnerable VBLB
dd V
Vdd
dd PUP1 PUP2 V
Vdd
dd
to noise during read operation 10 0
1
PG1 VL VR PG2
V Vwldd V PDN1 PDN2
Vdd wldd
BLB
+Vn- inv1
dd BL
VL1 0
VR
gnd

Internal node voltage [V] Bit-line voltage Vbl [V]

1.5
inv2 -Vn+ VBL
Write-trip point = 0.606V
1
VL
0.5
Vn = 0
+Vn Vn = SNM 0
0 0.2 0.4 0.6 0.8
Bit-line voltage Vbl [V]
1 1.2 1.4

1.5
-Vn VL
VR
1
VR
0.5

SNM: maximum dc noise 0

0 0.2 0.4 0.6 0.8 1 1.2 1.4
(Vn) (e.g. mismatches Bit-line voltage Vbl [V]

due to processing) that Write-trip point:

maximum Vbl at which cell
cell tolerates before its changes state
© imec 2006
changes state
Evelyn Grossar-TAD- 6
 Statistically-Aware Optimization of SRAM cell

Use a constraint algorithm together with dual-Vth

optimization algorithm to minimize the leakage power
of the cell

Constraint algorithm:
selects SRAM cell design which fulfills the delay and
functionality (read stability and write-ability) constraints

Minimization of leakage power SRAM cell

Vdd

0 0
BLB wl
Vdd wl
Vdd
BL
only sub-threshold
PUP1 PUP2 Vdd
Vdd
0 1 leakage current (Ids,sub) is
PG1 VL VR PG2 considered, due to
Ids,sub ~ exp(Vth)
PDN1 PDN2

gnd

© imec 2006 Evelyn Grossar-TAD- 7

 Outline

Introduction
Statistically Aware Optimization
Model distributions of performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 8

 Model distributions of performance parameters

Vth variability propagation to performance parameters

Distributions of performance parameters in function of Vth
e.g. SNM  2   2 SNM 2  2 SNM 2  2 SNM 2 
 SNM  SNM  0.5       
Vth , pupi   ,
  V 2
 i 1  th , pgi
Vth , pgi
 V 2 Vth , pdni
 V 2
th , pdni th , pupi 
2  
2 2 2
SNM  2  SNM  2  SNM  2
varSNM      Vth , pgi     Vth , pdni     Vth , pupi 
 
i 1  Vth , pgi 
   
  Vth , pdni   Vth , pupi  


Asymmetrical behavior of the SRAM cell with respect to internal

nodes Vl and Vr
f min( SNMhigh, SNMlow)  2 f SNM 1  FSNM 

Meeting the design constraint:

constraint SNM   SNM  3   SNM
98.987% of the total samples of the
SNM distribution fulfills the design constraint

© imec 2006 Evelyn Grossar-TAD- 9

 Outline

Introduction
Statistically Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 10

 Statistical sensitivities

Statistical sensitivity
gives information about direction and magnitude in which the
design parameter W has to move to improve the yield of the
design, which depends on the Vth intra-die variations
70
49.5% fulfills 100
60 the Wpg
SNM constraint Wpup
50 Wpdn
of 120mV for 80
Frequency

40 W pg=190nm

SNM yield [%]

30 60
20
slope =
40
statistical sensitivity
10

0
0.09 0.1 0.11 0.12 0.13 0.14 0.15
SNM [V] 70 20

60
29.8% fulfills 0
50 1.9 2 2.1 2.2 2.3 2.4
the SNM Transistor Width [m] -7
x 10
Frequency

constraint of
40
120mV for
30 W pg = 200nm

20

10

0
© imec 2006 Evelyn Grossar-TAD- 0.09 0.1 0.11 0.12 0.13 0.14 0.15 11
SNM [V]
 Outline

Introduction
Deterministic Method for SRAM Cell Optimization
Stability, delay and leakage power definition
Deterministic optimization approach
Worst-Case optimization approach
Results
Statistically Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 12

 Results compared with worst-case design
-3 -3 <<-3
worst-case design: +
p1 p2 
-sets all Vth parameters (p1, p2) to
their worst-case value with respect to performance parameter 
- overestimation of the underlying process variations
- increased power consumption and area
130nm statistical design:
-9
x 10 SNM Target = 120mV, Vwrite Target=0.4Vdd
1.85
worst case approach
- significant % over-design is
1.8 statistical optimization needed to fulfill the design targets
Standby leakage power [W]

1.75
with the worst-case approach
1.7
Iread Target Actual Iread Area
1.65
100uA 17% 27%
1.6
ca. 12%
ca.14% 170uA 10% 11%
1.55

- 14% degradation of leakage

1.5 ca. 40%

1.45
1 1.2 1.4 1.6 1.8 power SRAM cell results in 40%
Iread Target [A]
read current improvement
-4
x 10
© imec 2006 Evelyn Grossar-TAD- 13
 Outline

Statistically Aware Optimization

Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions

© imec 2006 Evelyn Grossar-TAD- 14

 Conclusions

 The optimization is based on an algorithm using

constraints and dual-Vth strategy:
 Including pdfs of the performance parameters
 Using statistical information to guide the optimization
 Results: - gain both in leakage power (11%) and area (27%) w.r.t
worst-case design
- trade-offs: improvements in read current (40%) of the cell
can be obtained by degrading leakage power (14%)

 Statistically aware circuit optimization proves to be

advantageous at cell level to keep both leakage power
consumption and area of the SRAM cell minimal

© imec 2006 Evelyn Grossar-TAD- 15

 Statistically Aware Optimization:
Results (3)

6
Iread Target = 130uA, SNM Target = 120mV, Vwrite Target = 0.4Vdd
3.5 x 10
worst-case approach
statistical approach
Total standby leakage power
distribution for an array matrix
3

2.5 of 16kB SRAM is approximated

mean = 178.41uW mean = 192.26uW
by a Gaussian distribution.
Frequency

2 sigma = 0.140uW sigma = 0.130uW

1.5

1
Central Limit Theorem states
0.5 that the sum of independent
0
identical distributions of any
1.7 1.75 1.8 1.85 1.9 1.95
Total standby leakage power [W]
2 2.05
x 10
-4 type approaches a normal
distribution

© imec 2006 Evelyn Grossar-TAD- 16

 Statistically-Aware Optimization of SRAM cell (2)

Compare with Worst-Case design approach:

-3 -3  <<-3

+
p1 p2 
- sets all Vth parameters (p1, p2) to their worst-case value
with respect to the performance parameter 
- overestimation of the underlying process variations
- increased power consumption and area
Delay constraint
Vdd
of SRAM cell:
BLB wl
Vdd
PUP1 PUP2
wl
Vdd
BL
Read current of weakest
1 0 SRAM cell mainly limits the
PG1 VL VR PG2 delay constraint
PDN1 PDN2
(first order approximation)
gnd
© imec 2006 Evelyn Grossar-TAD- 17