You are on page 1of 34

OPERATIONAL AMPLIFIERS

AND ITS APPLICATIONS


7/25/14 FET-MITS 1
Presented By :
Jagdeep Kaur Sahani
Enrl. No.-080546
CONTENTS

N!"#$%&!#N #' #P-()P

N*E"!N+ ()P,'E"

N#N -N*E"!N+ ()P,'E"

$''E"EN&E ()P,'E"

&)#S #P-()P

(PP,&(!#N #' #PE"(!#N(, ()P,'E"

&#N&,%S#N

"E'E"EN&ES
7/25/14 FET-MITS 2
INTRODUCTION

#riginally in.ented in early /040s using .a1uu2 tu3e


te1hnology.

nitial purpose 4as to e5e1ute 2ath operations in analog


ele1troni1 1al1ulating 2a1hines.

6ith in.ention o7 transistor8 #p-(2p is redu1ed in si9e .

:uge .ariety o7 appli1ations in ele1troni1s.

,o4 1ost8 and ease o7 2ass produ1tion 2a;e the2


e5tre2ely popular.

!hey are a.aila3le in on integrated 1ir1uit <&=.


7/25/14 FET-MITS 3
OPERATIONAL AMPLIFIER
7/25/14 FET-MITS 4
PIN DESCRIPTION

!he op-a2p is a 1hip8 >4/.

t has 8 pins or 1onne1tors .

#nly 5 are usually used.

Pin nu23er ? and @ are used 7or inputs.

Pin 6 is used 7or output.

Po4er supplies are gi.en at pin > <A= and 4 <-=.


7/25/14 FET-MITS 5
IDEAL OPERATIONAL AMPLIFIER
&ir1uit diagra2 o7 ideal op-a2p
7/25/14 FET-MITS 6

OPERATIONAL AMPLIFIER SPECIFICATIONS

+ain is in7inite Ba C D

nput resistan1e is in7inite B R


i C D

#utput resistan1e is 9ero B RO C 0

&o22on 2ode gain C 0

Sle4 "ate C D

Band4idth C D

$ri7t C 0
7/25/14 FET-MITS 7
BASIC STAGES OF OP-AMP

7/25/14 FET-MITS 8
Blo1; $iagra2 o7 #p-(2p
INPUT STAGE :

t has dual-input8 3alan1ed-output di77erential a2pli7ier.

t pro.ides a high gain and input i2pedan1e .

,arge 1o22on 2ode reEe1tion ratio and po4er supply


reEe1tion ratio.

,o4 o77set .oltage and noise.


INTERMEDIATE STAGE:

"eFuired 7or high gain.

t 1on.ert the di77erential signal to single ended signal.


7/25/14 FET-MITS 9
LEVEL SHIFTING STAGE:

(s dire1t 1oupling is used8 there is li2it in output s4ing .

!o shi7t the d1 le.el at the output o7 the inter2ediate stage


to 9ero .olts 4ith respe1t to ground.
OUTPUT STAGE:

t pro.ides the lo4 output i2pedan1e .

and larger output 1urrent needed to dri.e the load o7 op-


a2p.

!he output stage in1reases the output .oltage s4ing and


raises the 1urrent supplying 1apa3ility o7 the op-a2p.
7/25/14 FET-MITS 10
BASIC CONFIGURATIONS OF
OP-AMP

n.erting (2pli7ier

Non -n.erting (2pli7ier

$i77eren1e (2pli7ier
7/25/14 FET-MITS 11
INVERTING AMPLIFIER

!he positi.e end o7 the input .oltage *


in is 1onne1ted through a resistor
"/ to the in.erting input pin <-=.

!he nonin.erting input pin <A= is 1onne1ted to ground.

"? de1ides the gain o7 a2pli7ier.


7/25/14 FET-MITS 12
&ir1uit $iagra2 o7 n.erting (2pli7ier
CONTINUED.

!he output is 1lipped at saturation le.el 8 i7 ratio o7 "


?

and "/is too large.

t gi.es in1reased sta3ility8 3and4idth 8and lo4er noise

+ain is redu1ed.

!he gain A7 is de7ined as the ratio o7 the output to input .oltages.


7/25/14 FET-MITS 13
NON-INVERTING AMPLIFIER

nput .oltage *in is applied dire1tly to nonin.erting


ter2inal.

Negati.e 7eed3a1; is pro.ided 3y the t4o e5ternal resistors "


/ and
"? 4hi1h 7or2 a .oltage di.ider.
7/25/14 FET-MITS 14
&ir1uit $iagra2 #7 Non -n.erting (2pli7ier

'ra1tion o7 the output .oltage is 7eed 3a1; to the in.erting


input ter2inal .

!he gain o7 the a2pli7ier is deter2ined 3y the e5ternal


resistors "
/ and "? a11ording to the eFuation:
7/25/14 FET-MITS 15
DIFFERENCE AMPLIFIER

$i77eren1e 3et4een the t4o input signals is a2pli7ied.

"esistors 1onne1ted to *
/ G *? should ha.e the sa2e .alue .
!4o resistors8 1onne1ted to *out and ground8 should also ha.e the sa2e .alue.
7/25/14 FET-MITS 16
&ir1uit $iagra2 #7 $i77eren1e (2pli7ier
CMOS OP-AMP

H/-H5 :(1ti.e-loaded )#S di77erential pair8 .oltage gain


and high input resistan1e.

H6-H>:1o22on-sour1e a2pli7ier gi.es .oltage gain.

$& arrange2ent: 3ias 1urrent o7 the input stage pro.ided


3y H5 and 7or se1ond stage is pro.ided 3y H>.
7/25/14 FET-MITS 17
!4o-stage &)#S (2pli7ier
ADVANTAGES

t has high output .oltage s4ing.


DISADVANTAGES

t has a 1o2pro2ised 7reFuen1y response.

!his topology has high po4er 1onsu2ption 3e1ause o7 t4o


stages in its design.

So 4e ha.e to use 1as1ode 1on7iguration.

&as1ode topology to in1rease the gain o7 the input


di77erential pair.

'olded 1as1ode i2pro.es 7reFuen1y response and &)".


7/25/14 FET-MITS 18
APPLICATIONS OF
OPERATIONAL AMPLIFIER
7/25/14 FET-MITS 19
INVERTING SUMMING AMP
7/25/14 FET-MITS 20
&ir1uit $iagra2 #7 Su22ing (2pli7ier
%sing the .irtual ground rule 7or node ( and #h2Is la4 4e
ha.e:
&onsidering *o 8 4e ha.e
TRANSCONDUCTANCE AMP

t produ1es a 1urrent proportional to the input .oltage.

&urrent 7lo4s in the Z


f is proportional to the input .oltage Vs.

i7 #p-(2p has in7inite input i2pedan1e8 4e 4ill ha.e


7/25/14 FET-MITS 21
Basi1 !rans1ondu1tan1e (2pli7ier &ir1uit
CONTINUED.

( .oltage to 1urrent 1on.erter is an a2pli7ier

!he 1onstant o7 proportionality is usually 1alled


trans1ondu1tan1e.

t a1ts as .oltage 1ontrolled 1urrent sour1e.

t is a non in.erting #p-(2p s1he2e.

#utput i2pedan1e o7 the de.i1e is high.

%sed as 7ilters.
7/25/14 FET-MITS 22
TRANSRESISTANCE AMP

t has produ1es a .oltage proportional to the input 1urrent.

$ue to .irtual ground the 1urrent going through the shunt


resistan1e R
s is 9ero .

#utput .oltage a1ross the 7eed3a1; resistor Rf i.e.


Vo(t)=Rs is(t)
7/25/14 FET-MITS 23
Basi1 &on7iguration 7or a !ransi2pedan1e
#p-(2p
CONTINUED.

( 1urrent to .oltage 1on.erter is an a2pli7ier .

&onstant o7 proportionality is 1alled transi2pedan1e or


transresistan1e.

(ppli1ations are photo-2ultipliers photo-tu3es and


photodiodes 8 4hi1h are used in the produ1tion o7 solar
po4er and used as 1urrent sour1es.

t is used 7or lo4-po4er appli1ations to produ1e an output


.oltage proportional to the input 1urrent.
7/25/14 FET-MITS 24

!he output is proportional to the logarith2 o7 the input.

t is 2ounted as an in.erting a2pli7ier8 i7 *


i is positi.e8 then
diode is in 1ondu1tion. *o is negati.e .
7/25/14 FET-MITS 25
Sho4s a $iode Based ,ogarith2i1 (2pli7ier
LOGARITHMIC AMPLIFIER
!he diode 1hara1teristi1s is
&onsidering that a7ter so2e alge3ra 4e 7inally get
(s the BJ! 1olle1tor 1urrent Ic .ersus V
BE is also an e5ponential 1ur.e8 diode
1an 3e repla1ed 4ith an npn BJ! .
7/25/14 FET-MITS 26
BJ! 3ased ,ogarith2i1
(2pli7iers
ANTI-LOGARITHMIC AMPLIFIER

#utput is proportional to in.erse o7 logarith2 o7 the input.

$iode is used 4ith negati.e 7eed3a1;.

!he 1urrent 7lo4ing through the diode is gi.en as:


7/25/14 FET-MITS 27
%sing oh2Is la4 and diode 1urrent 8

!hus output .oltage is gi.en is:

6e 1an use BJ! to 2a;e anti-


logarith2i1 a2pli7ier .

t gi.es 3etter input range.

%sed to analog 2ultipliers and


di.iders.
7/25/14
FET-MITS 28
BJ! 3ased (nti-,ogarith2i1
(2pli7iers
ANALOG COMPARATOR
7/25/14 FET-MITS 29

(n #p-(2p 4ith no 7eed3a1; 3eha.es li;e a 1o2parator.

t has high gain and 4or;s in Saturation region.


7 *
i J *re78 then *o C A *sat

7 *i K *re78 then *o C L*sat


&o2parator 1ir1uit
VOLTAGE FOLLOWER

!he .oltage 7ollo4er is 2a;e using in.erting 1on7iguration .

7 ratio o7 resistors in in.erting 1on7iguration is 9ero8 unity


gain is a1hie.ed.

t is 1alled as 3u77er or 7ollo4er a2pli7ier.


7/25/14 FET-MITS 30
*oltage 'ollo4er
OTHER APPLICATIONS

#perational a2pli7iers are used to 2a;e di77erent types o7


7ilters li;e lo4 pass 7ilter8 high pass 7ilter8 2ulti-7eed3a1;
7ilters.

#perational (2pli7iers are also used as 2easuring de.i1es.

Pea; and pea;-to-pea; dete1tors

ntegrator

$i77erentiator

(nalog 2ultipliers and di.iders

Bio2edi1al de.i1es

n heating syste2
7/25/14 FET-MITS 31
CONCLUSION

#p-(2p are 3uilding 3lo1;s o7 analog ele1troni1 1ir1uits.

t is used in 1ontrol syste2s8 instru2entation8 signal


pro1essing . t also used as 7ollo4ing:

Sensor a2pli7i1ation

)athe2ati1al operations <su2s8 di77eren1e8 in.erse=

'ilters <:ighM,o4MBand pass=.

)easure2ent de.i1es

$ue to s1aling do4n o7 )#S'E! length and


supply .oltage 8designing o7 #p-(2p is
3e1o2ing 1hallenge.

6e ha.e to de.elop ne4 te1hniFues and 7ind ne4 ideas 7or


3etter per7or2an1e o7 operational a2pli7iers.
7/25/14 FET-MITS 32
REFERENCES

Ji2 Kar;i8 N%nderstanding #perational (2pli7ier Spe1i7i1ationsO P(PE": Mixed Signal and
Analog Operational Amplifiers Digital Signal Processing Soltions 6:!E S,#(0// (pril
/008.

Phillip E. (llen8 N&)#S (nalog &ir1uit $esignO8 <>M4M06= Page >.0-/. - ?006.

(yush +upta8 (ditya Bhansali8 S4ati Bharga.a8 Shruti Jain N&on7iguration o7 #perational
(2pli7ier using &)#SO Department of !lectronics and "ommnication !ngineering #a$pee
%ni&ersit$ of Information 'ec(nolog$) Solan.

*.K )ehta8 "ohit )ehta 8 prin1iple o7 ele1troni1s 8//


th edition 8?008.

Jas2ine8 $esign and analysis o7 &)#S !eles1opi1 #perational (2pli7ier N!hesis o7 )aster o7 S1ien1e8 (!lectronics * "ommnication) of '(apar Institte of
!ngineering * 'ec(nolog$ (Deemed %ni&ersit$)) Patiala..

Rama+ant A) ,a$+-ad ).Op/Amp and linear Integrated "ircits .fort( edition.

Sedra S2ith8 )i1roele1troni1s &ir1uits8 7ourth edition8 #57ord %ni.ersity Press.


7/25/14 FET-MITS 33
THANK YOU
vala!l" #$$"#%&'(#
7/25/14 FET-MITS 34

You might also like