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7/25/14 FET-MITS 2
INTRODUCTION
+ain is in7inite Ba C D
Sle4 "ate C D
Band4idth C D
$ri7t C 0
7/25/14 FET-MITS 7
BASIC STAGES OF OP-AMP
7/25/14 FET-MITS 8
Blo1; $iagra2 o7 #p-(2p
INPUT STAGE :
n.erting (2pli7ier
$i77eren1e (2pli7ier
7/25/14 FET-MITS 11
INVERTING AMPLIFIER
+ain is redu1ed.
"esistors 1onne1ted to *
/ G *? should ha.e the sa2e .alue .
!4o resistors8 1onne1ted to *out and ground8 should also ha.e the sa2e .alue.
7/25/14 FET-MITS 16
&ir1uit $iagra2 #7 $i77eren1e (2pli7ier
CMOS OP-AMP
%sed as 7ilters.
7/25/14 FET-MITS 22
TRANSRESISTANCE AMP
ntegrator
$i77erentiator
Bio2edi1al de.i1es
n heating syste2
7/25/14 FET-MITS 31
CONCLUSION
Sensor a2pli7i1ation
)easure2ent de.i1es
Ji2 Kar;i8 N%nderstanding #perational (2pli7ier Spe1i7i1ationsO P(PE": Mixed Signal and
Analog Operational Amplifiers Digital Signal Processing Soltions 6:!E S,#(0// (pril
/008.
Phillip E. (llen8 N&)#S (nalog &ir1uit $esignO8 <>M4M06= Page >.0-/. - ?006.
(yush +upta8 (ditya Bhansali8 S4ati Bharga.a8 Shruti Jain N&on7iguration o7 #perational
(2pli7ier using &)#SO Department of !lectronics and "ommnication !ngineering #a$pee
%ni&ersit$ of Information 'ec(nolog$) Solan.
Jas2ine8 $esign and analysis o7 &)#S !eles1opi1 #perational (2pli7ier N!hesis o7 )aster o7 S1ien1e8 (!lectronics * "ommnication) of '(apar Institte of
!ngineering * 'ec(nolog$ (Deemed %ni&ersit$)) Patiala..