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Architecture
Arithmetic
for Computers
Outline for the lectures
Some arithmetic fundamentals
Division of hardware into integer and floating
point computation
Designing an integer Arithmetic Logic Unit
(ALU) for MIPS
Integer addition
Integer multiplication
Integer division
Floating point representation
Floating point computation
MIPS floating point registers
MIPS floating point instructions
Some arithmetic fundamentals
Unsigned numbers: values are always positive
Example: 1000 10102 = 27+23+21=14610
Logical operations
AND, OR, NOR, XOR perform logic function on a bit-by-
bit basis
Example: 1000 1010 AND 1101 0110 = 1000 0010
Also arithmetic/logical shift left/right
Basic hardware building blocks
Integer and floating point
computation
Most general-purpose ISAs specify
separate integer and floating point register
files
Operandrepresentation formats differ
Computation hardware differs
flt pt
adder
flt pt
register
file
flt pt
multiplier
Recall the 604e microprocessor
integer register
file and
execution units
flt pt register
file and
execution units
Designing an integer ALU for MIPS
ALU = Arithmetic Logic Unit
Inputs
a,b:the data (operands) to be operated on
ALU operation: the operation to be performed
Outputs
Result: the result of the operation
Zero: indicates if the Result = 0 (for beq, bne)
CarryOut: the carry out of an addition operation
Overflow: indicates if an add or sub had an overflow (later)
Basic integer addition
Pencil-and-paper binary addition
(CarryIn)
a
b
(CarryOut) Sum
(LSB)
(MSB)
Less 3
Less 3
Set
Key elements
Examine multiplier bits from right to left
Shift multiplicand left one position each step
Simplification: each step, add multiplicand to running
product total, but only if multiplier bit = 1
Integer multiplication
32-bit hardware implementation
LSB
Example:
00111110 is equivalent to 01000000 –
00000010
requires additions for each of requires an addition for this
these bit positions bit position
00001101 0 (product+multiplier)
extra bit
position
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11101101 0
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00010110 1
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00001011 0
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00001011 0
+1110
11101011 0
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00001011 0
+1110
11110101 1
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00001011 0
+1110
11110101 1
Booth recoding
Example
0010 (multiplicand)
00001101 0
+1110
11110110 1
+0010
00001011 0
+1110
11111010 1 (product)
Integer division
Pencil and paper binary division
01000000
Integer division
Shift partial remainder left one position
10000000
Integer division
Subtract divisor from left half of partial
remainder
(divisor) 1000 10010000 (dividend) 0100 (quotient)
- 1000
00100000
- 1000
11010000
01000000
- 1000
11000000
10000000
- 1000
00000000
Integer division
Result positive, left shift 1 into quotient
10000000
- 1000
00000000 (remainder)
Integer division
Hardware implementation
What operations do
we do here?
flt pt
adder
flt pt
register
file
flt pt
multiplier
(-1)S x 1.M x BE
S E M
B=2
S E M
1 bit 8 bits 23 bits
Double precision (dp) format (“double” in C)
S E M
1 bit 11 bits 52 bits
IEEE 754 floating point standard
Exponent bias is 127 for sp and 1023 for dp
Sp form is
(-1)S x 1.M22 M21 …M0 x 2E-127
and value is
(-1)S x (1+(M22 x2-1 ) +(M21 x2-2 )+…+(M0x2-23 )) x 2E-127
Sp example
1 00000001 1000…000
S E M
Number is –1.1000…000 x 21-127 =-1.5 x 2-126 =1.763 x 10-38
IEEE 754 floating point standard
Denormalized numbers
Allow for representation of very small numbers
Smallest
positive dp denormalized number is
0.00…01 x 2-1022 = 2-2074
1 00000001 0000…01100
S E M
0 00000011 0100…00111
S E M
Floating point addition example
Identify smaller E and calculate E
difference
1 00000001 0000…01100
S E M
difference = 2
0 00000011 0100…00111
S E M
Floating point addition example
Shift smaller M right by E difference
1 00000001 0100…00011
S E M
0 00000011 0100…00111
S E M
Floating point addition example
Add mantissas
1 00000001 0100…00011
S E M
0 00000011 0100…00111
S E M
-0.0100…00011 + 1.0100…00111 =
1.0000…00100
0 0000…00100
S E M
Floating point addition example
Choose larger exponent for result
1 00000001 0100…00011
S E M
0 00000011 0100…00111
S E M
0 00000011 0000…00100
S E M
Floating point addition example
Final answer (already normalized)
1 00000001 0100…00011
S E M
0 00000011 0100…00111
S E M
0 00000011 0000…00100
S E M
Floating point addition
Hardware design
determine
smaller
exponent
Floating point addition
Hardware design
shift mantissa
of smaller
number right
by exponent
difference
Floating point addition
Hardware design
add mantissas
Floating point addition
Hardware design
normalize result by
shifting mantissa of
result and adjusting
larger exponent
Floating point addition
Hardware design
round result
Floating point addition
Hardware design
renormalize if
necessary