VLIW ARCHITECTURE

AND DATA ADDRESSING

VISHAL IYER (C016)
SAGAR SAWANT (C028)
PROF. SATWIK PATNAIK
INTRODUCTION
VLIW stands for VERY LONG INSTRUCTION WORD
As stated in Microprocessor Report(2/14/94):
"The objective of VLIW is to eliminate the complicated instruction scheduling and
parallel dispatch that occurs in most modern microprocessors. In theory, a VLIW
processor should be faster and less expensive than a comparable RISC chip."

WHY VLIW?
Until ~1997, most DSP processors were very similar
Specialized execution units.
Specialized instruction sets.
Difficult to program in assembly.
Unfriendly compiler targets.
One instruction per instruction cycle.

VLIW Architecture
It consist of multiple execution units.
It uses multiple instructions/cycle and use simple, regular instruction sets.
More parallelism, higher performance
Better compiler targets




VLIW ARCHITECTURE
VLIW in DSP
The mathematics of digital signal processing are well-suited for
a VLIW architecture.

In DSP the FFT operations require a lot of 'multiply/accumulate' operations. There
is a great deal of inherent parallelism in such operations, making them an ideal
candidate for a VLIW architecture.



ADVANTAGES OF VLIW ARCHITECTURE
Increased performance
Better compiler performance
Potentially easier to program
Potentially scalable
Can add more execution units, allow more instructions to be packed into the
VLIW instruction
DISADVANTAGES OF VLIW
New kinds of programmer/compiler complexity
-Programmer (or code-generation tool) must keep track of instruction
scheduling
-Deep pipelines and long latencies can be confusing, may make peak
performance elusive
Increased memory use
-High program memory bandwidth requirements
High power consumption
Misleading MIPS ratings
COMPARISONS
Execution time
COMPARISONS
MEMORY USAGE
ADDRESSING MODES
Immediate addressing
Indirect addressing
Register addressing
Direct addressing
Circular addressing

Immediate Addressing
It is used to handle constant data
Size of the data depends on registers 8,16or 32 bit
Example:
MOV AC0, #FFFFh
Indirect addressing
The instruction will specify that an auxiliary register holds the memory address
which in turn holds the data

Example:
ADD *AR1, *AR0, AC0


Register Addressing
The contents of a register is directly copied into another register.


Example:
MOV AC0,AC1

Direct Addressing

In this case the opcode will contain a memory address which holds the data
Example:
MOV @0005h,AC0
Circular Addressing
It is used in convolution, FIR filtering techniques
They use circular buffers which contain the most recent data to be processed
Registers used in circular addressing are
1 CBSR1
2 CBSR2
3 CBER1
4 CBER2
5 CBCR
Execution

Time n Time n+1 Time n+2 Time n+3
x(n-1) x(n-1) x(n+2) x(n+2)
x(n) x(n) x(n) x(n+3)
x(n-2) x(n+1) x(n+1) x(n+1)