ASIC DESIGN FLOW

Introduction

ASIC - Application Specific Integrated Circuit

In Integrated Circuit (IC) designed to perform a specific
function for a specific application

TYPES OF ASIC
Full custom:A full-custom IC includes some (possibly all)
logic cells that are customized and all mask layers that are
customized. A microprocessor is an example of a full-custom
IC.
Full-custom ICs are the most expensive to manufacture and to
design. The manufacturing lead time (the time it takes just to
make an ICnot including design time) is typically eight weeks
for a full-custom IC. These specialized full-custom ICs are
often intended for a specific application, so we might call some
of them full-custom ASICs.

 A cell-based ASIC (cell-based IC, or CBIC a common

term in Japan, pronounced sea-bick) uses predesigned logic
cells (AND gates, OR gates, multiplexers, and flip-flops, for
example) known as standard cells . We could apply the term
CBIC to any IC that uses cells, but it is generally accepted that
a cell-based ASIC or CBIC means a standard-cellbased
ASIC.

 1. Design entry - Using a hardware description

language ( HDL ) or schematic entry
2. Logic synthesis - Produces a netlist - logic
cells and their connections
3. System partitioning - Divide a large system
into ASIC-sized pieces
4. Prelayout simulation - Check to see if the
design functions correctly
5. Floorplanning - Arrange the blocks of the netlist
on the chip
6. Placement - Decide the locations of cells in a
block

7. Routing - Make the connections between cells

and blocks
8. Extraction - Determine the resistance and
capacitance of the interconnect

9. Postlayout simulation - Check to see the

design still works with the added loads of the
interconnect

Design Specification

What are the main design considerations?

Design feasibility?
Performance
power consumption
cost
Design spec?
Written (Document)
Good starting point, but can be misinterpreted by design
team
Executable (UML, C/C++, Behavioral VHDL,
SystemVerilog)
Harder to understand, less room for misinterpretation

RTL Specification
Determine I/O signals
Standard interface, protocol, custom interface
Partition design into functional blocks
Data path, Control logic, Memory, etc.
Determine block interfaces
Specify each block separately at RTL
MUXs, counters, adders, flip-flops etc.

Functional Simulation
Preparation for simulation
Generate simulation patterns
Waveform entry
HDL testbench

Generate simulation netlist

Functional simulation
To verify the functionality of your design only

Simulation results
Waveform display
Text output

Common pitfalls/important points

Do not start design entry until all details are clear
A poor design cannot be saved by good code and
synthesis/implementation constraints
Sometimes though, it is better to let the tool do the
optimization (for example state machines)