Universal Verification

Methodology

Santosh

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Introduction
UVM

provides the best framework to

achieve coverage-driven verification
(CDV)
The purpose of CDV is to:
Eliminate the effort and time spent
creating hundreds of tests.
Ensure thorough verification using upfront goal setting.
Receive early error notifications and
deploy run-time checking and error
analysis to simplify debugging.
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Typical Verification
Environment

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UVM Class Hierarchy

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UVM Base Classes

Uvm_object
Set of methods for such common operations as create,
copy, compare, print and record.
Root Base class for all objects in uvm environment

Uvm_transaction
Root base class for all UVM transactions.
Inheriting from uvm_object and adds timing & recording
interface.

Uvm_report_object
Provides reporting facility.
Components can issue various messages with different
severity levels
Configurable actions for individual messages from a
particular component or for all messages from all
components in the environment.
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UVM Base Classes(contd)

Uvm_component
Inherits all features of uvm_object,
uvm_reporting_class
Provides interfaces like hierarchy,
phasing, reporting, transaction recording,
factory

Uvm_root
Implicit top-level and phase controller for
all UVM components
An instance is automatically created
Supports other features like Searching
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UVM Factory
Used to manufacture (create) UVM objects and
components.
User defined objects and components are to be
registered with the factory by macros
uvm_component_registry #(T,Tname)
uvm_object_registry #(T,Tname)

The factory generates and stores lightweight

proxies to the user-defined objects for efficient
usage of Memory
Construction : objects and components registered
with factory are created using Create()
Overriding : All instances / types can be overriden
using methods of factory.
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Classes derived from

uvm_component
Uvm_test
Class to define all test-cases
These class names acts as inputs to run_test()

Uvm_driver
Ports to connect sequencer
Tasks to drive signals onto DUT

uvm_monitor
Connected to DUT for monitoring signals
Connected to analysis ports

Uvm_agent
Uvm_env
uvm_sequencer
serves as an arbiter for controlling transaction flow from
multiple stimulus generators
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Classes derived from

uvm_transaction

The uvm_sequence_base class provides the

interfaces needed to create streams of sequence
such as pre_body, body, post_body etc.,
Uvm_sequence is the base class for all user
defined sequences
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Sequencers
uvm_sequencer

#(REQ,RSP)

Requests for new sequence items are

initiated by the driver.
Returns a sequence from a list of available
sequence
Connected to uvm_driver

uvm_push_sequencer

#(REQ,RSP)

Sequence items are pushed to the driver

Driver blocks item flow when it is not ready
Connected to uvm_push_driver

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Sequencer Driver Interface

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Sequence Driver
interface

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UVM Reporting

Ex: virtualfunctionvoiduvm_report_info
(stringid,stringmessage,intverbosity=UVM_MEDIUM,stringfile
name="",intline=0)

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Transaction Core utilities

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Field Automation Flags

Example for registering transaction object :

`uvm_object_utils_begin(Packet)
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`uvm_field_int(da,UVM_ALL_ON|UVM_NOPACK)
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UVM Phases
New
Creates objects, basic initialization is done

Build
Configuration parameters are applied in creating child classes
All component which are constructed using Create function are created

Connect
Components are connected using TLM ports
All Binding Processes all port, export, and imp connections
Checks whether each ports min and max connection requirements are
met

End

of Elaboration

Override this method to perform any checks on the elaborated

hierarchy before the simulation phases begin

Start

of Simulation

Override this method to perform component- specific pre-run

operations, such as discovery of the elaborated hierarchy, printing
banners, etc.
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UVM Phases (Contd)

Run
Main body of the test is executed where all
threads are forked off

Extract
All the required information is gathered

Check
Check the results of the extracted information
such as un responded requests in scoreboard,
read statistics registers etc

Report
Reporting pass/fail status.
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Ubus Example
Ubus is a basic bus arbiter with
priority
Given example DUT supports 2
master with 0 having priority
over 1
Test-bench is designed for
configurable number of master
and slave agents, configurable
coverage and checks

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Verification Environment

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Protocol Phases

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 Define a transaction packet

Which extends from uvm_sequence_item

Define Interface for signal onto DUT

Define Master agent Define
Master Driver
Master Monitor
Master Sequencer

Slave agent Define Bus Monitor

Slave Driver
Slave Monitor
Slave Sequencer

Environment
Create an environment with given
parameters

Scoreboard
Test-case
Objects of environment and scoreboard are
created, and connected
A Test is run by selecting single/multiple
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sequences to generate the
stimulus