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MOS: Metal-Oxide-Semiconductor
Vg
Vg
gate
gate
metal
SiO2
SiO2
N+
Si body
MOS capacitor
N+
P-body
MOS transistor
Slide 5-1
P-Silicon body
SiO2
N +polysilicon
Ec
Ec
Ef , Ec
Ef
Ev
Ev
Gate
Si
Body
Ev
Slide 5-2
SiO2 =0.95 eV
Ec
qg
q s = Si + (Ec Ef )
3.1 eV Si
3.1 eV
=4.05eV
Ec, Ef
Ec
qVfb
Ev
N+ -poly-Si
E0 : Vacuum level
E0 Ef : Work function
E0 Ec : Electron affinity
Si/SiO2 energy barrier
9 eV
P-body
4.8 eV
Ef
Ev
V fb g s
Ev
SiO2
Slide 5-3
Vg V fb s Vox
Vox
Ec , Ef
Ev
E0
qVg
q s
Ec
Ef
Ev
is negligible
when is in
the surface
accumulation.
Slide 5-4
Vox Vg V fb
Vg <Vt
Gausss Law
Vox Qs / Cox
Slide 5-5
>
Vfb )
qVox
++++++
qVg
Wdep
depletion
region
Ec, Ef
charge, Q dep
P-Si body
Ev
Ef
Ev
--
SiO
-- -- -- -- -- -- -------depletion layer
Ec
q s
gate
qN a 2 s s
Qdep qN aWdep
Qs
Vox
Cox
Cox
Cox
Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-6
Vg V fb s Vox V fb s
qN a 2 s s
Cox
Slide 5-7
Ec
st
st 2B 2 ln
q ni
qVg = qVt
Ei
C =q
A
D
Ec, Ef
Ev
kT N v kT N v kT N a
q B
( E f Ev ) |bulk
ln
ln
ln
2
q ni
q Na
q ni
Eg
Slide 5-8
Ef
Ev
Threshold Voltage
Vg Vfb s Vox
At threshold,
kT N a
st 2B 2 ln
q ni
Vox
qN a 2 s 2 B
Cox
qN a 2 s 2B
Vt Vg at threshold V fb 2B
Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-9
Threshold Voltage
Vt (V), P+ gate/N-body
V t(V), N + gate/P-body
Tox = 20nm
Cox
ody
T = 20nm
+ for P-body,
for N-body
ox
Modern Semiconductor Devices for Integrated
Circuits (C. Hu)
ody
Vt V fb 2 B
qN sub(a)2 s 2 B
Slide 5-10
Wdep Wdmax
2 s 2 B
qN a
Vg > Vt
gate
---
++++++++++
SiO
- - - - - - - -
- - - - - - Q dep
Qinv
P - Si substrate
Ec
Ef
Ev
qVg
Ec, Ef
Ev
Slide 5-11
Qdep
Cox
qN a 2 s 2B Qinv
Qinv
V fb 2B
Cox
Cox
Cox
Qinv
Cox
Vg > Vt
Slide 5-12
Slide 5-13
2B
Vt
Vg
inversion
Wdep
Wdmax
Wdmax = (2s2 q a
s)1/2
accumulation Vfb
depletion
Vt
inversion
Vg
Slide 5-14
accumulation
depletion
(a)
inversion
0 Vt
qNaWdep
Vg
qNaWdmax
Qinv
Qs
accumulation depletion
(b)
Vfb
Vt
inversion
Vg
accumulation
regime
depletion
regime
inversion
regime
slope = Cox
Vfb
Qacc
Qinv
slope = Cox
(c)
Vfb
Vg
0 Vt
slope = Cox
Vt
accumulation depletion
inversion
Vg
Slide 5-15
dQg
dQs
C
dVg
dVg
MOS Capacitor
C-V Meter
Slide 5-16
dQg
dQs
C
dVg
dVg
Qs
accumulation depletion
regime
regime
inversion
regime
Cox
Vfb
Vg
0 Vt
Qinv
slope = Cox
V
Vt
accumulation fb depletion
inversion
Slide 5-17
Vg
CV Characteristics
Cox
Vfb
accumulation
depletion
Vt
Vg
inversion
1
1
1
C Cox Cdep
1
1 2(Vg V fb )
2
C
Cox
qN a s
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-18
gate
Cox
Cox
+++++ ++++
C
- - - - - dep
- Wdep
Accumulation
Depletion
P-substrate
P-substrate
gate
gate
Cox
N+
- - - - - - - -
Inversion
DC and AC Wdmax
P-substrate
DC
AC
Cox
- - - - - - - - -
- -
Cdmax- -
Inversion Wdmax
P-substrate
In each case, C = ?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-19
Slide 5-20
accumulation
Vfb
depletion
Vt
Vg
inversion
The quasi-static CV is obtained by the application of a slow linearramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very
sensitive DC ammeter. C is calculated from Ig = CdVg/dt. This allows
sufficient time for Qinv to respond to the slow-changing Vg .
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-21
(Answer: QS CV).
(Answer: QS CV).
Slide 5-22
E
Vfb0
Ev
gate
oxide body
(a)
Ef, Ec
Vfb
Ev
gate
+
+
+
oxide body
(b)
Slide 5-23
Slide 5-24
20 nm
30 nm
Tox
0.15V
0.3V
What does it tell us? Body work function? Doping type? Other?
Solution: V fb g s QoxTox / ox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-25
from intercept
g s 0.15 V
E0 , vacuum level
s = g + 0.15V
Ef , Ec
Ec
Ef
Ev
Ev
N+ -Si gate
Si body
0.15 eV kT
1017 cm -3
N-type substrate, N d n N c e
from slope
Qox 1.7 10 8 C / cm 2
Slide 5-26
Gausss Law
1
1
C
ox C poly
P+ poly-Si
Cpoly
Co x
P+
Ec
Ef
++++++++
N-body
Ev
(b)
P+
Tox Wdpoly
s
ox
ox
Tox Wdpoly / 3
If Wdpoly= 15 , what is the
effective increase in Tox?
Slide 5-27
P+ -gate
Ev
N-substrate
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-28
19
2 10 7cm 1.6 10 19 C 8 10 cm
1.3 nm
Slide 5-29
Wdpoly
2 s poly
qN poly
2
dpoly qN polyWdpoly
/ 2 s 0.11 V
kT N c
1.1 V 0.15 V 0.95 V
V fb
ln
q
q Nd
Vg 0.95 V 0.85 V 1 V 0.11 V 1.01 V
Eg
Slide 5-30
Gate
poly-Si
depletion
region
Tinv
SiO2
Si
Quantum
mechanical theory
10
20
30
40
50 A
Physical Tox
Effective T o
x
Slide 5-31
Slide 5-32
Basic CV
with poly-depletion
with poly-depletion and
charge-layer thickness
measured data
Vg
Slide 5-33
Cox
Co x
Cdep
Cp oly
Cox
Co x
Cdep
Cin v
(a)
General case for
both depletion and
inversion regions.
Cdep, min
(b)
In the depletion
regions
Cinv
Cinv
(c)
Vg Vt
(d)
Strong inversion
Slide 5-34
Ec
Ef
--
Ev
Ec, E f
Ec , Ef
Ev
Ev
(a)
(b)
Exposed to light
Slide 5-35
- - - - -
depletion region
oxide
- - -
- - - - - -
P-Si
V2 > V1 > V3
V1
V2
- - - - -
(b)
V3
V1
V3
V2
V1
oxide
depletion region
- - -
P-Si
V1
V2
V3
V1
V2
V3
V1
V2 > V1 = V3
(c)
- - - - -
depletion region
oxide
- - -
P-Si
Slide 5-36
Signal out
Reading row,
shielded from light
Charge-to-voltage converter
Slide 5-37
switch
V1
Amplifier
circuit
V2
V3
Shifter circuit
Signal out
Slide 5-38
V fb g s (Qox / Cox )
Vg V fb s Vox poly
V fb s Qs / Cox poly
Slide 5-39
st 2 B or ( B 0.45 V)
kT N sub
B
ln
q
ni
qN sub 2 s | st |
Vt V fb st
Cox
+ : N-type device, : P-type device
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-40
A c c u m u l a ti o n
F la t-b a n d
V g < V fb < 0
E f V g = V fb< 0
Ef
N-type Device EE ff
(N+-gate over P-substrate)
V g 0 > V fb
Ef
Ef
Ef
P-type Device
(P+-gate over N-substrate)
EE ff
F la t-b a n d
D ep letio n
V g = V fb < 0
Ef
V g > V fb > 0
V g = V fb > 0
Ef
Ef
V g = V fb > 0
Ef
V g 0 < V fb
Ef
Ef
Ef
D ep letio n
V g 0 > V fb
E f V g = V t> 0
V g 0 < V fb
Vg=Vt<0
T h r e s h o ld
Ef
Ef
Ef
Ef
Ef
Ef
Ef
T h r e s h o ld
I n v e r si o n g
Ef
V g > V t> 0
Ef
Vg Vt
f
Modern Semiconductor Devices
for Integrated
E f Circuits (C. Hu)
Ef
Slide 5-41
Ef
P-type Device
QS CV
Transistor CV
Capacitor
(HF) CV
Vg
Vg
Slide 5-42