Ch. 6 Lecture Slides For Chenming Hu Book: Modern Semiconductor Devices For ICs

Chapter 6 MOSFET
The MOSFET (MOS Field-Effect Transistor) is the

building block of Gb memory chips, GHz
microprocessors, analog, and RF circuits.
Match the following MOSFET characteristics with their
applications:
small size
high speed
low power
high gain
Modern Semiconductor Devices for Integrated Circuits (C.

Hu)
Slide 6-1
6.1 Introduction to the MOSFET

Basic MOSFET structure and IV characteristics

Hu)
Slide 6-2
6.1 Introduction to the MOSFET

Two ways of representing a MOSFET:

Hu)
Slide 6-3
Early Patents on the Field-Effect Transistor

Hu)
Slide 6-4
Early Patents on the Field-Effect Transistor
In 1935, a British patent was issued to Oskar Heil.

A working MOSFET was not demonstrated until 1955.
Using todays terminology, what are 1, 2, and 6?
Hu)
Slide 6-5
6.2 MOSFETs Technology

Polysilicon gate and 1.2nm SiO2
1.2 nm SiO2 used in production. Leakage current through the

oxide limits further thickness reduction.
Hu)
Slide 6-6
6.2 Complementary MOSFETs Technology

NFET
PFET
When Vg = Vdd , the NFET is on and the PFET is off.

When Vg = 0, the PFET is on and the NFET is off.
Hu)
Slide 6-7
CMOS (Complementary MOS) Inverter

Vd d
PFET
Vin
S
D
Vo ut
D
NFET
S
0V
C:
capacitance
(of interconnect,
0V etc.)
A CMOS inverter is made(a)

of a PFET pull-up device and a
NFET pull-down device. Vout = ? if Vin = 0 V.
Hu)
Slide 6-8
CMOS (Complementary MOS) Inverter

Vdd
P+
Vin
P+
Vout
N
Vdd
P
PFET
N-well
0V
Contact
N-well
P-substrate
Vin
Vout
NFET
(b)
NFET and PFET can be fabricated

on the same chip.
N+
0V
(c)
basic layout
of a
CMOS inverter

Hu)
Slide 6-9
6.3 Surface Mobilities and High-Mobility FETs

6.3.1 Surface Mobilities
Vg = Vdd , Vgs = Vdd
Vds > 0
Ids
How to measure the surface mobility:
I ds W Qinv v WQinv nsE WQinv nsVds / L

WCoxe (Vgs Vt ) nsVds / L
Hu)
Slide 6-10
Mobility is a function of the average of the fields at the

bottom and the top of the inversion charge layer, Eb and Et .
From Gausss Law,
Eb = Qdep/s
Vt V fb st Qdep / Coxe
Therefore,
Eb
Coxe
(Vt V fb st )
s
Et (Qdep Qinv ) / s
Eb Qinv / s Eb
C
oxe (Vgs V fb st )
s
Coxe
(Vgs Vt )
s
C
1
( Eb Et ) oxe (Vgs Vt 2V fb 2 st )
2 s
2
Coxe
(Vgs Vt 0.2 V)
2 s
Vgs Vt 0.2 V
6Toxe

Hu)
Slide 6-11
Universal Surface Mobilities

(Vgs + V t + 0.2)/6Toxe (MV/cm)
Surface mobility (cm2 /V-s)
(NFET)
Surface roughness
scattering is stronger
(mobility is lower) at
higher Vg, higher Vt, and
thinner Toxe.
(PFET)
(Vgs + 1.5V t 0.25)/6Tox e (MV/cm)

Hu)
Slide 6-12
EXAMPLE: What is the surface mobility at Vgs=1 V

in an N-channel MOSFET with Vt=0.3 V and Toxe=2
nm?
Solution:
(Vgs Vt 0.2) / 6Toxe

1.5 V / 12 10 7 cm
1.25 MV/cm
1 MV is a megavolt (106 V). From the mobility figure,

ns=190 cm2/Vs, which is several times smaller than
the bulk mobility.

Hu)
Slide 6-13
6.3.2 GaAs MESFET

source
N
gate
metal
N-channel
drain
N
GaAs
Semi-insulating substrate
MESFET IV characteristics are similar to MOSFETs but

does not require a gate oxide.
Question: What is the advantage of GaAs FET over Si FET?
Terms: depletion-mode transistor, enhancement-mode transistor
Hu)
Slide 6-14
6.3.3 HEMT, High Electron Mobility Transistor

N-GaAlAs
source
+
metal gate
drain
.......
Undoped GaAs
A large-Eg semiconductor serves as the gate dielectric.

The layer of electrons is called 2D-electron-gas, the equivalent
of the inversion or accumulation layer of a MOSFET.
Hu)
Slide 6-15
6.3.4 JFET
source
N
P+ gate
N-channel
drain
N
P-Si
The gate is a P+N junction.

The FET is a junction field-effect transistor (JFET).

Hu)
Slide 6-16
6.4 Vt and Body Effect

How to Measure the Vt of a MOSFET
A
B
Method A. Vt is measured by extrapolating the Ids versus

W
Vgs curve to Ids = 0.
I dsat Coxe (Vgs Vt ) nsVds Vgs Vt
L
Method B. The Vg at which Ids =0.1A W/L
Hu)
Slide 6-17
MOSFET Vt and the Body Effect

Two capacitors => two
charge components
Cdep
Wd max
Qinv Coxe (Vgs Vt ) CdepVsb

Coxe
Cdep
Cdep
Coxe (Vgs (Vt
Vsb ))
Coxe
Redefine Vt as
Vt (Vsb ) Vt 0
Cdep
Coxe
Vsb Vt 0 Vsb

Hu)
Slide 6-18
MOSFET Vt and the Body Effect

Body effect: Vt is a function
of Vsb. When the source-body
junction is reverse-biased,
Vt increases.
Vt (V)
NFET
0.4
Vt 0
0.6
model
data
0.2
0
Vs b (V)
-0.2
PFET

= Cdep/Coxe
= 3Toxe / Wdep
-1
-0.4 Vt0
Vt Vt 0 Vsb
-2
Body effect coefficient:
-0.6
Body effect slows down circuits? How can it be reduced?

Hu)
Slide 6-19
Retrograde Body Doping Profiles

Vt (V)
Wdmax for retrograde doping
NFET
0.6
model
data
0.4
Vt 0
0.2
-2
-1
Vs b (V)
-0.2
Wdmax for uniform doping
-0.4 Vt0
PFET
-0.6
Wdep does not vary with Vsb .

Retrograde doping is popular because it reduces off-state
leakage and allows higher surface mobility.
Hu)
Slide 6-20
Uniform Body Doping

When the source/body junction is reverse-biased, there are
two quasi-Fermi levels (Efn and Efp) which are separated by
qVsb. An NMOSFET reaches threshold of inversion when Ec
is close to Efn , not Efp . This requires the band-bending to be
2B + Vsb , not 2B.
qN a 2 s
Vt Vt 0
( 2 B Vsb 2 B )
Coxe
Vt 0 ( 2 B Vsb 2 B )
is the body-effect parameter.

Hu)
Slide 6-21
6.5 Qinv in MOSFET
Channel voltage
Vc=Vs at x = 0 and
Vc=Vd at x = L.
Qinv = Coxe(Vgs Vcs Vt0 (Vsb+Vcs)

= Coxe(Vgs Vcs (Vt0 +Vsb) Vcs)
= Coxe(Vgs mVcs Vt)
m 1 += 1 + 3Toxe/Wdmax
m is called the body-effect factor or bulk-charge factor
Hu)
Slide 6-22
6.6 Basic MOSFET IV Model

Ids= WQinvv= WQinvnsE
= WCoxe(Vgs mVcs Vt)nsdVcs/dx
Vds
I ds dx WCoxe ns (Vgs mVcs Vt )dVcs

0
IdsL = WCoxens(Vgs Vt mVds/2)Vds
W
m
I ds Coxe s (Vgs Vt Vds )Vds
L
2

Hu)
Slide 6-23
Vdsat : Drain Saturation Voltage
dI ds
W
0 Coxe ns (Vgs Vt mVds )
dVds
L
Vdsat

Hu)
Vgs Vt
m
Slide 6-24
ds
= V
d sa t
Vcs
V
d s
= V
d sa t
(e )
dsat
L
inv
> V
Vcs
(a )
ds
= C
o x
(V
m V c s V t )
(b )
d s
d sa t
L
inv
(f)
I = nQ
in v
dV
cs
0
I = nQ
/d x
(c )
(d)
in v
dV
cs
/d x
(g )
Id
Ec so u r c e
Id
sa t
0
E
sa t
- - -
s o u rc e
d ra in
(h )
Vds Vdsat
d ra in

Hu)
Slide 6-25
Saturation Current and Transconductance
linear region, saturation region

I dsat
Coxe ns (Vgs Vt ) 2
2mL
transconductance: gm= dIds/dVgs
g msat
Coxe ns (Vgs Vt )
mL

Hu)
Slide 6-26
6.7.1 CMOS Inverter--voltage transfer curve
Vo ut (V)
V dd
2.0
1.5
1.0
0.5
Vdd
0.5
1.0
1.5

Hu)
2.0
Vin (V)
Slide 6-27
6.7.2 Inverter Speed propagation delay

Vdd
V1
...........
V2
V3
............
V2
Vdd
2 d
V3
V1
0
d : propagation delay
Hu)
Slide 6-28
6.7.2 Inverter Speed - Impact of Ion

1
d ( pull down delay
2
CVdd
pull up delay
2 I onP
pull down delay
CVdd
2 I onN
pull up delay )
Vdd
Vin
Vout
CVdd 1
1
d
(
)
4 I onN I onP
How can the speed of an inverter circuit be improved?
Hu)
Slide 6-29
Logic Gates
V dd
AB
A
B
This two-input NAND

gate and many other
logic gates are
extensions of the
inverter.
Hu)
Slide 6-30
6.7.3 Power Consumption

Pdynamic Vdd average current k CVdd2 f
Vdd
Pstatic Vdd I off

Total power consumption
Vin
Vout
P Pdynamic Pstatic

Hu)
Slide 6-31
6.8 Velocity Saturation

ns E
v
E
1
Esat
E << Esat : v = nsE
E >> Esat : v =
ns Esat
Velocity saturation has
large and deleterious
effect on the Ion of
MOSFETS
Hu)
Slide 6-32
6.9 MOSFET IV Model with Velocity Saturation
I ds WQinv v
ns dVcs / dx
I ds WCoxe (Vgs mVcs Vt )
dV
1 cs / Esat
dx
Vds
I ds dx 0 [WCoxe ns (Vgs mVcs Vt ) I ds / Esat]dVcs
I ds L WCoxe ns (Vgs Vt
m
Vds )Vds I dsVds / Esat
2

Hu)
Slide 6-33
W
m
Coxe ns (Vgs Vt Vds )Vds
L
2
I ds
Vds
1
Esat L
long - channel I ds
I ds
1 Vds / Esat L

Hu)
Slide 6-34

Solving
Vdsat
dI ds
0,
dVds
2(Vgs Vt ) / m
1 1 2(Vgs Vt ) / mEsat L
A simpler and more accurate Vdsat is:

1
Vdsat
m
1
Vgs Vt Esat L
Esat
2vsat
ns

Hu)
Slide 6-35
EXAMPLE: Drain Saturation Voltage

Question: At Vgs = 1.8 V, what is the Vdsat of an NFET with
Toxe = 3 nm, Vt = 0.25 V, and Wdmax = 45 nm for (a) L =10 m,
(b) L = 1 um, (c) L = 0.1 m, and (d) L = 0.05 m?
Solution: From Vgs , Vt , and Toxe , ns is 200 cm2V-1s-1.
Esat= 2vsat/ns = 8 104 V/cm
m = 1 + 3Toxe/Wdmax = 1.2
Vdsat
m
1
Vgs Vt Esat L

Hu)
Slide 6-36
EXAMPLE: Drain Saturation Voltage
Vdsat
m
1
Vgs Vt Esat L
(a) L = 10 m, Vdsat= (1/1.3V + 1/80V)-1 = 1.3 V

(b) L = 1 m,
Vdsat= (1/1.3V + 1/8V)-1 = 1.1 V
(c) L = 0.1 m, Vdsat= (1/1.3V + 1/.8V)-1 = 0.5 V

(d) L = 0.05 m, Vdsat= (1/1.3V + 1/.4V)-1 = 0.3 V
Hu)
Slide 6-37
Idsat with Velocity Saturation

Substituting Vdsat for Vds in Ids equation gives:
I dsat
long - channel I dsat

(
V
V
)
W
gs
t
Coxe s
Vgs Vt
Vgs Vt
2mL
1
1
mEsat L
mEsat L
Very short channel case:
Esat L Vgs Vt
I dsat Wv sat C oxe (V gs Vt mEsat L )

I dsat Wv sat C oxe (V gs Vt )
Idsat is proportional to VgsVt rather than (Vgs Vt)2 , not
as sensitive to L as 1/L.
Hu)
Slide 6-38
0.1
V gs = 1.0V
Measured MOSFET
IV
0.0
0
0.4
I ds (mA/m)
L = 0.15 m
V gs = 2.5V
Vt = 0.4 V
0.3
V gs = 1.5V
V gs = 1.0V
Vgs = 2.0V
0.01
Vgs = 1.5 V
Vgs = 1.0V
0.0
0.03
Vgs = 2.5 V
L = 2.0 m
0.02
0.2
0.0
V ds (V)
2.5
Vds (V)
What is the main difference between the Vg dependence

Vgs = 2.5 V
L = 2.0 m
of the long- and short-channel length IV curves?
V = 0.7 V
t
m)
0.02
2.5
Vt = 0.7 V
V gs = 2.0V
0.1
V ds (V)
0.03
(b)
Ids (A/m)

Hu)
Slide 6-39
PMOS and NMOS IV Characteristics
The PMOS IV is qualitatively similar to the NMOS IV,

but the current is about half as large. How can we
design a CMOS inverter so that its voltage transfer
curve is symmetric?
Hu)
Slide 6-40
6.9.1 Velocity Saturation vs. Pinch-Off

Current saturation : the carrier velocity reaches Vsat
at the drain.
Instead of the pinch-off region, there is a velocity
saturation region next to the drain where Qinv is a
constant (Idsat/Wvsat).

Hu)
Slide 6-41
6.10 Parasitic Source-Drain Resistance
If Idsat0 Vg Vt , I dsat
I dsat 0
I R
1 dsat 0 s
(Vgs Vt )
Idsat can be reduced by about 15% in a 0.1m MOSFET.

Effect is greater in shorter MOSFETs.
Vdsat = Vdsat0 + Idsat (Rs + Rd)
Hu)
Slide 6-42
SALICIDE (Self-Aligned Silicide) Source/Drain

contact metal
dielectric spacer
gate
oxide
channel
N+ source or drain
NiSi 2 or TiSi2
After the spacer is formed, a Ti or Mo film is deposited. Annealing causes

the silicide to be formed over the source, drain, and gate. Unreacted metal
(over the spacer) is removed by wet etching.
Question:
What is the purpose of siliciding the source/drain/gate?
What is self-aligned to what?
Hu)
Slide 4-43
Definitions of Channel Length

Ldraw n
Lg
N
N
L, L eff ,
or Le
L Lg L
Hu)
Slide 6-44
6.11 Extraction of the Series Resistance and the

Effective Channel Length
I ds
WCoxe sVds
(Vgs Vt )
Ldrawn L
I (L
L)
Vds ds drawn
WCoxe (Vgs Vt ) s
Vds

Ids
Include series resistance,

Rds Rd + Rs ,
Vds
Ldrawn L
Rds
I ds
WCoxe (Vgs Vt ) s
data
300
intercept
Vgs Vt = 1 V
200
Vg s Vt = 2 V
100
Rd s
Ldrawn (m)

Hu)
Slide 6-45
6.12 Velocity Overshoot
Velocity saturation
should not occur in very
short MOSFETs.
This velocity overshoot
could lift the limit on Ids .
But

Hu)
Slide 6-46
6.12 Source Velocity Limit

Carrier velocity is limited
by the thermal velocity
with which they enter the
channel from the source.
Idsat = WBvthxQinv
= WBvthxCoxe(Vgs Vt)
Similar to

Hu)
Slide 6-47
6.13 Output Conductance

Idsat does NOT saturate in the saturation region, especially
in short channel devices!
The slope of the Ids-Vds curve in the saturation region is
called the output conductance (gds),
0.4
(a)
A smaller gds is desirable for a

large voltage gain, which is
beneficial to analog and digital
circuit applications.
L = 0.15 m
I ds (mA/m)
g ds
dI dsat
dVds
V gs = 2.5V
Vt = 0.4 V
0.3
V gs = 2.0V
0.2
V gs = 1.5V
0.1
V gs = 1.0V
0.0
0
V ds (V)
0.03
Modern Semiconductor Devices for Integrated
Circuits (C.
(b)
Hu)
L = 2.0 m
2.5
Slide 6-48
Vgs = 2.5 V
Example of an Amplifier
The transistor operates in the saturation region. A small
signal input, vin, is applied.
ids g msa t gs g ds ds
Vdd
g msa t in g ds out
ids out / R
out
g msat
in
(g ds 1/ R )
R
in
out
NFET
The voltage gain is gmsat/(gds + 1/R).

A smaller gds is desirable for large voltage gain.
Maximum available gain (or intrinsic voltage gain) is gmsat/gds
Hu)
Slide 6-49
6.14 High-Frequency Performance

D
Cutoff frequency (fT) : Frequency at

which the output current becomes equal
to the input current.
Rd
Rin
G
Low Frequency
Model
High-frequency performance is limited

by input R and/or C.
Maximum oscillation frequency

(fmax) : Frequency at which the power
gain drops to unity
Rs
S
Rin Rg electrode Rii
Gate-electrode resistance
Intrinsic input resistance

Hu)
Slide 6-50
Gate-Electrode Resistance
Drain
Source
Rg-electrode
Multi-finger layout greatly reduces

the gate electrode resistance
Rg electrode W / 12Tg Lg N f
: resistivity of gate material,
Wf : width of each gate finger,
Tg : gate thickness,
Lg : gate length,
Nf : number of fingers.
Hu)
Slide 6-51
Intrinsic Input Resistance

G
Rg-electrode
C ox
RG c h
ch
V dsat
Vds
Rii dRch
I ds
The gate capacitor current flows through Rch to the

source and ground.
Hu)
Slide 6-52
6.15 MOSFET Noises

Noise : All that corrupts the signal
External noise:
Inductive and capacitive interferences and cross
talks created by wiring
Needs to be controlled with shielding and circuit
layout carefully
Fundamental noise:
Noise inherent to the electronic devices.
Due to the random behaviors of the electric
carriers inside the device
Hu)
Slide 6-53
6.15.1 Thermal Noise of a Resistor

Thermal noise: caused by
random thermal motion of the
charge carriers
S(f)
S : noise power density

spectrum

Hu)
Slide 6-54
6.15.2 MOSFET Thermal Noise

i
vds2
C ox
S
2
d
V d sa t
2
g
ids2
vds2 4kTf / g ds
G
S
ids2 4kTfg ds
Parasitic-resistance noise
B
Hu)
Slide 6-55
6.15.3 MOSFET Flicker Noise

Charge trapping and releasing
by a single oxide trap generate
Random Telegraph Noise
ET= EF
Vg = 0.85V
RTS Waveform
Trap filled half the time

0
250
500
750
1m
1E-16
KF W I ds AF
i
( ) kTf
2
fL Cox W
2
ds
of 100 samples
1E-18 Average
1/f where = 1 + a/ = 1.15
id
S (A / H
z)
Time (s)
Many traps produce a 1/f

power density spectrum.
1/f noise
W/L = 10 m/0.28 m
-1
a = 0.17A
Model representation of measurement
1E-20
10
100
1k
10k
Frequency (Hz)

Hu)
Slide 6-56
6.15.4 Signal to Noise Ratio, Noise Factor,

Noise Figure
SNR: Signal power noise power.
Decibel or dB:10 times the base-10 logarithm of the
noise power.
S
10 log
Noise factor: The ratio of the input SNR and output

SNR.
S /N
F
S0 / N 0

Hu)
Slide 6-57
6.16 Memory Devices

Keep
Cell size
data
and
without cost/bit
power?
Rewrite
cycles
SRAM
No
Large
Unlimited Fastest Totally
Embedded in
logic chips
DRAM
No
Small
Unlimited Fast
Needs
modification
Stand-alone
main memory
Smallest
Limited
Needs
extensive
modification
Nonvolatile
data and code
storage

Hu)
Slide 6-58
Flash
Yes
memory
(NVM)
Writeonebyte
speed
Slow
Compatible
with basic
CMOS
fabrication
Main
applications
6.16.1 SRAM
>Fastest among all
memories.
>Totally CMOS
compatible.
>Cost per bit is the
highest-- uses 6 transistors
to store one bit of data.

Hu)
Slide 6-59
6.16.2 DRAM
Word-line 1 Word-line 2
Bit-line 1
Bit-line 2
DRAM capacitor
can only hold the data
(charge) for a limited
time because of
leakage current.
Needs refresh.
Needs ~10fF C in a
small and shrinking
area -- for refresh time
and error rate.

Hu)
Slide 6-60
6.16.2 DRAM capacitor technology
Stacked capacitor and

Trench capacitor
Hu)
Slide 6-61
6.16.3 Nonvolatile (Flash) Memory
Floating gate
(poly-Si)
Charge trap
(SONOS)
Nanocrystal
Hu)
Slide 6-62
Phase Change Memory
Alloy of Ge, Sb, Te has high resistivity in

amorphous phase and low resistivity in
polycrystalline phase.

Hu)
Slide 6-63
3D (Multi-layer) Memory
Epitaxy from seed windows can produce Si layers.
Ideally memory element is simple and does not need
single-crystalline material.

Hu)
Resistive Memory (RRAM)

-- Organic, inorganic, metallic.. material
-- Future extension to 3-D

Hu)
6.17 Chapter Summary

propagation delay
CVdd 1
1
d
(
)
4 I onN I onP
Power Consumption
P kCVdd2 f Vdd I off

body effect
Vt (Vsb ) Vt 0 Vsb
for steep retrograde body doping
3Toxe / Wdmax
Hu)
Slide 6-66

basic Ids model
W
m
I ds Coxe s (Vgs Vt Vds )Vds
L
2
m 1 3Toxe / Wdmax 1.2

Small and m are desirable. Therefore, small Toxe is good.
Ch.7 shows that large Wdmax is not acceptable.
CMOS circuit speed is determined by CVdd/Idsat , and its
power by CVdd2f + VddIoff .
Hu)
Slide 6-67

IV characteristics can be divided into a linear region
and a saturation region.
Ids saturates at:
Vdsat
I dsat
Vgs Vt
transconductance:
m
W
Coxe s (Vgs Vt ) 2
2mL
g msat
Coxe s (Vgs Vt )
mL
Considering velocity saturation,

Vdsat
m
1
Vgs Vt Esat L
I dsat
long - channel I dsat
Vgs Vt
1
mEsat L

Hu)
Slide 6-68

At very small L
Velocity overshoot can lift vsat , but source velocity limit sets a
similar top over Idsat .
Idsat = WBvthxCoxe(Vgs Vt)
Intrinsic voltage gain is gmsat/gds
High fT and fMAX need low
Vds
Rii
I ds
Rin Rg electrode Rii
Rg electrode N f
Noise arises from the channel, gate, substrate thermal noises,

and
the flicker noise.
Hu)
Slide 6-69

SRAM, DRAM, Nonvolatle memory

Hu)
Slide 6-70

Ch. 6 Lecture Slides For Chenming Hu Book: Modern Semiconductor Devices For ICs

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Ch. 6 Lecture Slides For Chenming Hu Book: Modern Semiconductor Devices For ICs

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Chapter 6 MOSFET

The MOSFET (MOS Field-Effect Transistor) is the

Modern Semiconductor Devices for Integrated Circuits (C.

6.1 Introduction to the MOSFET

Modern Semiconductor Devices for Integrated Circuits (C.

6.1 Introduction to the MOSFET

Modern Semiconductor Devices for Integrated Circuits (C.

Early Patents on the Field-Effect Transistor

Modern Semiconductor Devices for Integrated Circuits (C.

Early Patents on the Field-Effect Transistor

In 1935, a British patent was issued to Oskar Heil.

6.2 MOSFETs Technology

1.2 nm SiO2 used in production. Leakage current through the

6.2 Complementary MOSFETs Technology

When Vg = Vdd , the NFET is on and the PFET is off.

CMOS (Complementary MOS) Inverter

A CMOS inverter is made(a)

CMOS (Complementary MOS) Inverter

NFET and PFET can be fabricated

Modern Semiconductor Devices for Integrated Circuits (C.

6.3 Surface Mobilities and High-Mobility FETs

How to measure the surface mobility:

I ds W Qinv v WQinv nsE WQinv nsVds / L

Mobility is a function of the average of the fields at the

Modern Semiconductor Devices for Integrated Circuits (C.

Universal Surface Mobilities

Surface mobility (cm2 /V-s)

(Vgs + 1.5V t 0.25)/6Tox e (MV/cm)

EXAMPLE: What is the surface mobility at Vgs=1 V

(Vgs Vt 0.2) / 6Toxe

1 MV is a megavolt (106 V). From the mobility figure,

Modern Semiconductor Devices for Integrated Circuits (C.

6.3.2 GaAs MESFET

MESFET IV characteristics are similar to MOSFETs but

6.3.3 HEMT, High Electron Mobility Transistor

A large-Eg semiconductor serves as the gate dielectric.

The gate is a P+N junction.

Modern Semiconductor Devices for Integrated Circuits (C.

6.4 Vt and Body Effect

Method A. Vt is measured by extrapolating the Ids versus

MOSFET Vt and the Body Effect

Qinv Coxe (Vgs Vt ) CdepVsb

Modern Semiconductor Devices for Integrated Circuits (C.

MOSFET Vt and the Body Effect

Body effect coefficient:

Body effect slows down circuits? How can it be reduced?

Retrograde Body Doping Profiles

Wdmax for retrograde doping

Wdmax for uniform doping

Wdep does not vary with Vsb .

Uniform Body Doping

is the body-effect parameter.

6.5 Qinv in MOSFET

Qinv = Coxe(Vgs Vcs Vt0 (Vsb+Vcs)

6.6 Basic MOSFET IV Model

I ds dx WCoxe ns (Vgs mVcs Vt )dVcs

IdsL = WCoxens(Vgs Vt mVds/2)Vds

Modern Semiconductor Devices for Integrated Circuits (C.

Vdsat : Drain Saturation Voltage

Modern Semiconductor Devices for Integrated Circuits (C.

Modern Semiconductor Devices for Integrated Circuits (C.

Saturation Current and Transconductance

linear region, saturation region