Professional Documents
Culture Documents
version
ARMv7
ARM1156T2F-S
ARM1136JF-S
ARMv6
ARM102xE XScale
TM
ARM1176JZF-S
ARM1026EJ-S
ARMv5
ARM9x6E ARM926EJ-S
SC200
ARM92xT
ARM7TDMI-S StrongARM
V4
SC100
1994
1996
ARM720T
1998
2000
2002
2006
2004
time
Processor Modes
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
spsr
FIQ
IRQ
SVC
Undef
Abort
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
Exception Handling
0x0C
FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort
0x08
Software Interrupt
0x04
Undefined Instruction
0x1C
0x18
0x14
0x10
Reset
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family devices
28 27
N Z C V Q
f
039v12
24
23
16 15
I F T
mode
c
T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Mode bits
Specify the processor mode
039v12
ARM instructions can be made to execute conditionally by postfixing them with the
appropriate condition code field.
This improves code density and performance by reducing the number of forward
branch instructions.
CMP
BEQ
ADD
skip
r3,#0
skip
r0,r1,r2
CMP
r3,#0
ADDNE r0,r1,r2
By default, data processing instructions do not affect the condition code flags but
the flags can be optionally set by using S. CMP does not need S.
loop
SUBS r1,r1,#1
BNE loop
Condition Codes
The possible condition codes are listed below
Note AL is the default and does not need to be specified
Suffix
EQ
NE
CS/HS
CC/LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Description
Equal
Not equal
Unsigned higher or same
Unsigned lower
Minus
Positive or Zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Greater or equal
Less than
Greater than
Less than or equal
Always
Flags tested
Z=1
Z=0
C=1
C=0
N=1
N=0
V=1
V=0
C=1 & Z=0
C=0 or Z=1
N=V
N!=V
Z=0 & N=V
Z=1 or N=!V
ARM instructions
unconditional
conditional
CMP r0, #0
CMP r0, #0
BNE else
ADDEQ r1, r1, #1
ADD r1, r1, #1
ADDNE r2, r2, #1
B end
...
else
ADD r2, r2, #1
end
...
5 instructions
5 words
5 or 6 cycles
3 instructions
3 words
3 cycles
10
ADC
EOR
CMN
MOV
SUB
BIC
TST
MVN
SBC
RSB
RSC
TEQ
Operand
1
Operand
2
Barrel
Shifter
number of positions
12
13
r6, #0
2. MOVS
r7,r7
r7,r7,#0
; if neg, r7=0-r7
RSBMI
3. ADD
RSB
r9,r8,r8,LSL #2
; r9=r8*5
r10,r9,r9,LSL #3
; r10=r9*7
14
Immediate constants
No ARM instruction can contain a 32 bit immediate constant
All ARM instructions are fixed as 32 bits long
The data processing instruction format has 12 bits available for
operand2
11
8 7
rot
x2
0
immed_8
Shifter
ROR
Quick Quiz:
0xe3a004ff
MOV r0, #???
Rule to remember is
8-bits rotated right by an even number of bit positions
15
instruction:
LDR rd, =const
This will either:
Produce a MOV or MVN instruction to generate the value (if possible).
or
Generate a LDR instruction with a PC-relative address to read the
constant from a literal pool (Constant data area embedded in the code).
For example
LDR r0,=0xFF =>
MOV r0,#0xFF
LDR r0,=0x55555555 =>
LDR r0,[PC,#Imm12]
DCD 0x55555555
This is the recommended way of loading constants into a register
16
STR Word
LDRB
STRB Byte
LDRH
STRH Halfword
Address accessed
18
Load/Store Exercise
Assume an array of 25 words. A compiler associates
y with r1. Assume that the base address for the array
is located in r2. Translate this C
statement/assignment using just three instructions:
array[10] = array[5] + y;
19
LDR
ADD
r3, r3, r1
STR
r3, [r2, #10]
array[10]
; r3 = array[5]
; r3 = array[5] + y
; array[5] + y =
20
Syntax:
<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>
4 addressing modes:
LDMIA / STMIA
increment after
LDMIB / STMIB
increment before
LDMDA / STMDA decrement after
LDMDB / STMDB decrement before
IA
IB
DA
DB
r4
r4
r1
r1
r0
r0
Increasing
Address
r4
r1
r4
r0
r1
r0
21
Branch instructions
Branch : B{<cond>} label
Branch with Link : BL{<cond>} subroutine_label
31
28 27
Cond
25 24 23
1 0 1 L
Offset
Link bit
0 = Branch
1 = Branch with link
Condition field
The processor core shifts the offset field left by 2 positions, sign-extends it
and adds it to the PC
32 Mbyte range
How to perform longer branches?
23
Register Usage
Register
Register variables
Must be preserved
Scratch register
(corruptible)
Stack Pointer
Link Register
Program Counter
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9/sb
r10/sl
r11
r12
r13/sp
r14/lr
r15/pc
24
B <label>
BL <subroutine>
039v12
func1
func2
STMFD sp!,
{regs,lr}
BL func1
BL func2
LDMFD sp!,
{regs,pc}
:
:
:
:
MOV pc, lr
25
PSR access
31
28 27
N Z C V Q de
24
23
mode
c
10
16 15
GE[3:0] IT cond_abc E A I F T
19
MRS r0,CPSR
BIC r0,r0,#0x80
MSR CPSR_c,r0
In User Mode, all bits can be read but only the condition flags (_f) can be modified
26
Agenda
Introduction to ARM Ltd
Fundamentals, Programmers Model, and Instructions
27
ARM7TDMI
Instruction
Fetch
ThumbARM
decompress
FETCH
ARM decode
Reg Select
DECODE
Reg
Read
Shift
ALU
Reg
Write
EXECUTE
ARM9TDMI
Instruction
Fetch
ARM or Thumb
Inst Decode
Reg
Reg
Decode
Read
FETCH
DECODE
Shift + ALU
EXECUTE
Memory
Access
Reg
Write
MEMORY
WRITE
28
FETCH
ARM or
Thumb
Instruction
Decode
ISSUE
Reg Read
DECODE
Shift + ALU
Memory
Access
Multiply
Multiply
Add
EXECUTE
MEMORY
Reg
Write
WRITE
ARM11
Fetch
1
Fetch
2
Decode
Issue
Shift
ALU
Saturate
MAC
1
MAC
2
MAC
3
Address
Data
Cache
1
Data
Cache
2
Write
back
29
Agenda
Introduction to ARM Ltd
Fundamentals, Programmers Model, and Instructions
Core Family Pipelines
AMBA
30
16 bit RAM
32 bit RAM
Interrupt
Controller
nIRQ
8 bit ROM
039v12
nFIQ
I/O
Peripherals
ARM
Core
31
AHB
High-bandwidth
on-chip RAM
APB
Bridge
UART
Timer
Keypad
PIO
DMA
Bus Master
High Performance
Pipelined
Burst Support
Multiple Bus Masters
039v12
APB
Low Power
Non-pipelined
Simple Interface
32
AHB Structure
Arbiter
HADDR
HWDATA
HADDR
Master
#1
HWDATA
HRDATA
Slave
#1
HRDATA
Address/Control
Master
#2
Slave
#2
Write Data
Read Data
Slave
#3
Master
#3
Slave
#4
Decoder
039v12
33