CMOS DESIGN METHODS

Design methodologies (general)

Three domains
Behavioral
Structural
physical
Three levels inside
Architectural
Logic/RTL
Physical

Evaluation of an I.C:

Performance speed, power, function, flexibility

Size of the die
Time to design i.e cost of engineering
Easy of verification, test generation and
testability

Design principles

Hierarchy
Regularity
Modularity
Locality

Hierarchy
Divide and conquer
Divide in modules and repeating untill
each submodule is comprehensible
prebuilt component available
Virtual components IP

Regularity
Similar submodules
All level of design hierarchy: equal size
transistors, standard cell type library,
parameterized RAM, etc.
Design reuse

Modularity
Well defined functions and interfaces
Interaction with other modules well characterized
Behavioral, structural and physical interfaces
(function, signals, electrical and timing
constraints)

Locality
Well characterized interfaces for the
modulecorrespond to reduce global
variables in HDL
Advantage for the clock

Design methods

Microprocessor/DSP
Programmable logic
Gate Array and Sea of Gates
Cell-based
Full custom
Platform-based design (SoC)

Programmable logic
Chips with Programmable logic structure
Chips with Programmable interconnects
Chips with Programmable gate arrays

Programmable logic structure

Programmable array logic (AND OR)
Vertical inputs, Selectively connected to
AND OR gate
Horizontal product terms
AND OR gate feed IO cell
Feed back

PAL

 PLD as a Black Box

Inputs

(logic variables)

Logic gates
and
programmable
switches

Outputs

(logic functions)

Programmable Logic Array (PLA)

x1 x2

Use to implement
circuits in SOP form
The connections in
the AND plane are
programmable
The connections in
the OR plane are
programmable

xn

Input buffers
and
inverters
x1 x1

xn xn
P1

AND plane

Pk

OR plane

f1

fm

Gate Level Version of PLA

x1

x2

x3
Programmable
connections

f1 = x1x2+x1x3'+x1'x2'x3

P1

OR plane

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

AND plane
f1

f2

x1

x2

x3

Example Schematic of a PAL

f1 = x1x2x3'+x1'x2x3
P1

f2 = x1'x2'+x1x2x3

P2

f1

P3
P4

AND plane

f2

 Limitations of PLAs
PLAs come in various sizes
Typical size is 16 inputs, 32 product terms, 8 outputs
Each AND gate has large fan-in this limits the number of inputs that can be
provided in a PLA
16 inputs 316 = possible input combinations; only 32 permitted (since 32
AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates as well
This makes PLAs slower and slightly more expensive than some
alternatives to be discussed shortly
8 outputs could have shared minterms, but not required

 Comparing PALs and PLAs

PALs have the same limitations as PLAs (small number of
allowed AND terms) plus they have a fixed OR plane less
flexibility than PLAs
PALs are simpler to manufacture, cheaper, and faster (better
performance)
PALs also often have extra circuitry connected to the output of
each OR gate
The OR gate plus this circuitry is called a macrocell

 Macrocell

Select

OR gate from PAL

0
1

Flip-flop
Clock

back to AND plane

Enable
f1

 Macrocell Functions
Enable = 0 can be used to allow the output pin for f 1 to be used as an
additional input pin to the PAL
Select

Enable = 1, Select = 0 is normal

for typical PAL operation
Enable = Select = 1 allows
the PAL to synchronize the
output changes with a clock
pulse

0
1

D Q
Clock

back to AND plane

The feedback to the AND plane provides for multi-level design

Enable
f1

 Multi-Level Design with PALs

f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'
where g = BC + B'C' and C = h below
A

B
Sel = 0

En = 0

D Q
Sel = 0

Clock

0
1

En = 1

D Q
Select

Clock

0
1

D Q
Clock

22V10

12 inputs
10 I/Os
Product terms 9 10 12 14 16 14 12 10 8
24 pins
AMD introduced the 22V10
Allowed register bypassing.

All of this has been bipolar and fuses to

this point

components

Register
4:1 MUX
Tristate buffer
2:1 MUX

CLK to output 8ns

Input to combinational output 15ns

Programmable Logic: PAL

Connections of
planes are realized
with fuses or
EPROM or
EEPROM

22V1
0
PAL

 Programming SPLDs
PLAs, PALs, and ROMs are also called SPLDs Simple Programmable
Logic Devices
SPLDs must be programmed so that the switches are in the correct places
CAD tools are usually used to do this
A fuse map is created by the CAD tool and then that map is downloaded to the device via a
special programming unit

There are two basic types of programming techniques

Removable sockets on a PCB
In system programming (ISP) on a PCB
This approach is not very common for PLAs and PALs but it is quite common for more
complex PLDs

Different ways to progam PAL

Fusible links
UV erasable EPROM
EEPROM

Fusible links

PROM
fusible-link MROM
custom programmed
by user
OTP (One Time
Programmable)
properties: Once
programmed, it
cannot be erase.

Typical Logic Diagram

Erasable Programmable ROM

(EPROM)
When Program
need special voltage (typically 10-25V)
used amount time (typically 50 msec)

Erasable: by Ultraviolet (UV) light

examples
2732 : 4K x 8 NMOS EPROM
2764 : 8K x 8

Flash stores the data by removing or putting

electrons on its floating gate . Charge on floating
gate affects the threshold of the memory element.
When electrons are present on the floating gate,
no current flows through the transistor, indicating
a logic-0. When electrons are removed from the
floating gate, the transistor starts conducting,
indicating a logic-1. This is achieved by applying
voltages between the control gate and source or
drain

Electrically Erasable PROM (EEPROM)

Erase by Electrically (high voltage) eg. 21v
generated from 5v
Write faster than PROM (5usec)
During Write, internal circuitry
automatically erases the cell
Former from Intel ex. 2816, 2864

 An SPLD Programming Unit

The SPLD is removed from the PCB, placed into the unit and
programmed there

 Removable SPLD Socket Package

PLCC (plastic-leaded chip carrier)

PLCC socket soldered to

the PCB

PROM-Type Array

Full-PLA Array

What Function is This?

16L8
PAL

Counter
design in
16R4 PAL

Programmable Logic: FPGA

Sea of Gates

Uninterrupted lines of Pand N diffusions

Metal interconnects over non used transistors
Lines are interrupted connecting PMOS to Vdd and NMOS to Vss
2-5 masks till three levels of metals, vias, interconnects

Cell-based
SSI
Memory
System level modules (processors, serial
interfaces, etc.
Mixed signal modules
Possible automatic generation of MSI modules
Option for power (1X, 2X, 4X.) and inputs

Full custom
Symbolic layout (old place transistors, wires,
contacts with graphic editor)
Silicon compilation: HDL that give all the views
of a project, i.e. behavior, timing, logical
Placement in a standard cell layout

Platform-based design (SoC)

Processors, memory, I/O functions, FPGA
Use of IP, hw/sw codesign

Design Flows
From behavioral specifications
to layout
Front end till RTL synthesis
Back end from structural
specifications to Physical synthesis
and layout

ASIC Design flow

Fig. 8.39

Automated Layout Generation

Fig. 8.41

Layout Design: Timing

Fig. 8.43

Design Economics
Stotal=Ctotal/(1-m)
Stotal : Selling price
Total cost
Non-recurring engineering costs
Recurring engineering costs
Fixed costs

Non-recurring engineering costs

Ftotal=Etotal+Ptotal
Engineering costs
Personnel cost (architectural design, logic, simulation,
layout, timing, DRC, test)
Prototype manufacturing costs
Computer
CAD software
Education
Costs (per annum): Personnel $150 K,computer $ 10K,
CAD tools (digital back end) $ 1 M shared

NREs - Prototyping
Mask cost
Test fixture cost
Package tooling
Values:
Mask set for 130 nm about $500-1000
Test fixture $ 1000-50.000

Recurring costs
Cost of single IC after the development phase
Rtotal=Rprocess+Rpackage+Rtest
Rprocess=W/(NxYwxYpa)
W = wafer cost (500-3000 $)
N=Number die
Yw=Die yield (70-90 %)
=Packaging yield (95-99%)

Fixed costs
Data sheets
Application notes
Marketing and commercial costs

In 1970, Texas Instruments developed a maskprogrammable IC based on the IBM read-only associative
memory or ROAM. This device, the TMS2000, was
programmed by altering the metal layer during the
production of the IC. The TMS2000 had up to 17 inputs
and 18 outputs with 8 JK flip flop for memory. TI coined
the term Programmable Logic Array for this device.[2]
A programmable logic array (PLA) has a programmable
AND gate array, which links to a programmable OR gate
array, which can then be conditionally complemented to
produce an output.