Sequential Logic

Topics

Asynchronous counter
Synchronous counter
Design of synchronous counter
Counter applications

Counter
Counter a group of flip-flops that are connected together to perform
counting operations.
Counters are categorized into two categories based on the way they
are clocked:
Asynchronous counter (or known as ripple counters)
the first flip-flop is clocked by the external clock pulse and then each
successive flip-flop is clocked by the output of the preceding flip-flop
do not have a common clock pulse
flip-flops within the counter do no change states at exactly the same
time

Synchronous counter
the clock input is connected to all the flip-flops so that they are
clocked simultaneously by a common clock pulse

Asynchronous counters

2 bit asynchronous binary counter

CLK is applied to the clock input (C) of the first flip-flop, FF0. FF0 is
always the least significant bit (LSB).
The Q0 output of FF0 is connected to the clock input of FF1.
Due to the propagation delay of the flip-flop, a transition of the input clock
pulse (CLK) and Q0 output can never occur simultaneously asynchronous
Assume the FFs are
initially RESET
Clk no

Clk Q0

/Q0 Q1

LSB

Since it goes through a binary

sequence, it is called a binary counter

2 bit asynchronous binary counter cont

The positive-going edge of CLK1 (clock pulse 1) causes the Q0 output of
FF0 to go HIGH and /Q0 to go LOW but this has no effect on FF1 because
positive-going transition must occur to trigger FF1. (Q0 = 1, Q1 = 0)
The positive-going transition of CLK2 causes Q0 to go LOW. The output /Q0
goes HIGH and triggers FF1, causing Q1 to go HIGH. (Q0 = 0, Q1 = 1)
The positive-going edge of CLK3 caused Q0 to go HIGH. The output /Q0
goes LOW and this has no effect on FF1 (Q0= 1, Q1 = 1)
The positive-going edge of CLK4 causes Q0 to go LOW. The output /Q0
goes HIGH and triggers FF1, causing Q1 to go LOW. (Q0 = 0, Q1 = 0)

3 bit asynchronous binary counter

Assume the FFs are initially RESET
No.

Clk

Q0

/Q0

Q1

/Q1

Q2

4 bit asynchronous binary counter

Assume the FFs

are initially
RESET

Clk no.

Clk

Q0 Q1 Q2 Q3

Clk no.

Clk

Q0

Q1 Q2 Q3

10

11

12

13

14

15

16

4 bit asynchronous binary counter cont

Propagation delay
Asynchronous counters are known as ripple counters because the effect of
the input clock pulse does not affect all the outputs of the flip-flops
simultaneously but ripples through the counter due to propagation delay.

Q1 is delayed by 1 delay

Q2 is delayed by 2 delays

Q3 is delayed by 3 delays

Propagation delay cont

The cumulative delay of an asynchronous counter is a major disadvantage
especially in high speed applications because it limits the rate at which the
counter can be clocked and creates decoding problems.
The maximum cumulative delay in a counter must be less than the period of
the clock waveform

Modulus of a counter
modulus of a counter number of unique states through which the counter will
sequence
maximum modulus the maximum possible of states of a counter is 2n, where n
is the number of flip-flops in the counter
truncated sequence the number of states with a sequence less than the
maximum of 2n
decade counter a counter with ten states in their sequence (MOD10). A
common modulus for counters
binary coded decimal (BCD) decade counter a decade counter with a count
sequence of zero (0000) through (1001). The ten-state sequence produce the
BDC code
to obtain a truncated sequence, it is necessary to force the counter to recycle
before going through all its possible states (e.g. a BCD counter must recycle back
to 0000 after 1001 state)

4 bit asynchronous decade counter

Assume the FFs are initially RESET

Clk pulse CLK Q0 Q1 Q2 Q3

/CLR

10

10

Q1 and Q3 are connected to a

NAND gate inputs to decode
the count of ten (1010)
because non of the other states
(zero through nine) have Q1
and Q3 HIGH at the same time
When counter goes into count
ten (1010), the output of the
NAND gate goes LOW and
resets all the flip-flops

4 bit asynchronous decade counter cont ..

glitch

glitch
A glitch on Q1 waveform because Q1 must first go HIGH before the count of
ten can be decoded. When the counter goes into the count of ten (1010), the
output of the NAND gate goes LOW.
Thus, the counter is in the 1010 state for a short time before it is RESET to
0000, thus producing a glitch on Q1 and /CLR line.
Show how an asynchronous counter can be implemented having a modulus
of 14 with a straight binary sequence from 0000 through 1101.

Answer
An asynchronous counter having a modulus of 14 with a
straight binary sequence from 0000 through 1101.

74LS93 asynchronous binary counter

consists of a single flip-flop and a 3-bit asynchronous counter.
can be used as a divide-by-2 device if only the single flip-flop is used, or it
can be used as a modulus-8 counter if only the 3-bit counter portion is used.
RO(1) and RO(2) - gated reset inputs. When both of these inputs are HIGH,
the counter is reset to the 0000 state /CLR.
divide-by-2 device

Logic diagram

modulus-8 counter

74LS93 asynchronous binary counter cont

The 74LS93 can be used as a 4-bit modulus-16 counter (counts 0 through
15) by connecting the Q0 output to the CLK B input as shown in (a).
It can also be configured as a decade counter (counts 0 through 9) with
asynchronous recycling by using the gated reset inputs for partial decoding
of count ten (1010), as shown in (b)
Immediately after the counter goes to count 10 (1010), it is reset to 0000.
The recycling, however, results in a glitch on Q1 because the counter must
go into the 1010 state for several nanoseconds before recycling.
Q3 = MSB
Q0 = LSB

(a)

(b)

Question: How do you connect the 74LS93 as a modulus-14 counter ?

Answer

2-bit synchronous binary counter

The flip-flops are initially RESET.
When the clock triggers the flipflops, there is a propagation delay
before the output of the flip-flops
make a transition.

counter

Timing details

2-bit synchronous binary counter cont

1. Determine
the flip-flop
input equations

2. Put the counter in an

arbitrary state; then determine
the inputs for this state.

3. Use the new inputs

to determine the next
state:

No Clk Outputs Flip-flops inputs

Q1 Q0 J1 = K1 = Q0

4. Set up the next

group of inputs from
the current output.

At the next clock pulse

J0 = K0 =1

J1 = K1

J0 = K0

NC

Toggle

Toggle

Toggle

NC

Toggle

Toggle

Toggle

NC

Toggle

Timing diagram

3-bit synchronous binary counter

Counter

Timing diagram

4 bit synchronous binary counter

flip-flop input equations

1. Determine
the flip-flop
input equations

No.

2. Put the counter in an

arbitrary state; then determine
the inputs for this state.

3. Use the new inputs

to determine the next
state:

Outputs

4. Set up the next

group of inputs from
the current output.

Flip-flops inputs

Q0 Q1 Q2 Q3

J0 = K0 = 1

J1 = K1 = Q0

J2 = K2 = Q0Q1

J2 = K2 = Q0Q1Q2

4 bit synchronous binary counter cont

1. Determine
the flip-flop
input equations

No.

2. Put the counter in an

arbitrary state; then determine
the inputs for this state.

3. Use the new inputs

to determine the next
state:

Outputs

4. Set up the next

group of inputs from
the current output.

Flip-flops inputs

Q 0 Q1 Q2 Q 3

J0 = K0 = 1

J1 = K1 = Q0

J2 = K2 = Q0Q1

J2 = K2 = Q0Q1Q2

10

11

12

13

14

15

16

4 bit synchronous binary counter cont

4 bit synchronous decade counter cont

Detects the occurrence of 1001 and causes the
counter to recycle on the next clock pulse

Clk

Outputs

Flip-flops inputs

Q0 Q1 Q2 Q3 J0 = K0 = 1

J1 = K1 = Q0Q3

J2 = K2 = Q0Q1

J2 = K2 =
Q0 Q1 Q2 + Q0 Q3

B4

4 bit synchronous decade counter cont

Clk

Outputs

Flip-flops inputs

Q0 Q1 Q2 Q3 J0 = K0 = 1

J1 = K1 = Q0Q3

J2 = K2 = Q0Q1

J2 = K2 =
Q0 Q1 Q2 + Q0 Q3

10

No glitch is observed
in Q1 waveform for
the synchronous
decade counter

4 bit synchronous decade counter cont

FF0 (Q0) toggles on each clock
pulse, so J0 = K0 = 1.
FF1 (Q1) changes on the next
clock pulse each time Q0 = 1 and
Q3 = 0, so J1 = K1 = Q1Q3.
FF2 (Q2) changes on the next
clock pulse each time both Q0 =
1 and Q1 = 1, so J2 = K2 = Q0Q1.
FF3 (Q3) changes on the next
clock pulse each time both Q0 =
1, Q1 = 1 and Q2 = 1 or when Q0
= 1 and Q3 = 1, so J2 = K2 =
Q0Q1Q2 + Q0Q3.

74HC163 synchronous binary counter

This counter can be synchronously preset to any 4-bit binary number by applying
the proper levels to the parallel data inputs.
When a LOW is applied to the LOAD input, counter will assume the state of the
data inputs on the next clock pulse. Thus, the counter sequence can start with any 4bit binary number.
An active-LOW CLR input synchronously resets all four flip-flops in the counter.
The two enable inputs, ENP and ENT must both be HIGH for the counter to
sequence through its binary states.
The ripple clock output (RCO) goes HIGH when the counter reaches the last state in
its sequence of fifteen, called the terminal count (TC = 15). This output, in
conjunction with the enable inputs, allows these counters to be cascaded for higher
count sequences.

Question:
How do you connect this counter to
count from 4 to 11?

Timing signal of 74HC163

Design of synchronous counters

The followings are the general steps used to design a

synchronous counter
1)
2)
3)
4)

obtain the state diagram for the counter

obtain the state table (transition table)
choose the type of flip-flops to be used
from the state table, obtain the required input for each
flip-flop to produce the next state for the given present
state based on the flip-flop excitation table
5) obtain the simplified flip-flop input equations and/or
output equations from the Karnaugh maps
6) implement the counter

State diagram
A graphical representation of the progression of states through which the
circuit advances when it is clocked
For example, the state diagram for a 3-bit up/down binary counter that
counts from the binary states of 0 to 7 when X (user selection) is HIGH and
counts from binary states of 7 to 0 when X is LOW is
Directed line
(transition from
the present state to
the next state)
Input during
present state
(labeled along the
directed line)

State (binary number

represents the state of
the flip-flops)

State diagram of a 3-bit up/down binary counter

State diagram cont

A state diagram contains the following elements:
a state is represented by a circle. The binary numbers inside each circle
identify the state of the flip-flops.
a transition from the present state to the next state is represented by a
directed line connecting the circles.
input value during the present state is labeled along each directed line.
output value
if the output is only dependent on the present state, the output is
labeled after the present state inside the circle and is preceded by a
slash (/) Mealy circuit.
if the output is dependent on the present state and the given inputs, the
output is labeled after the input along the directed line between the
states and is preceded by a slash (/) Moore circuit.

state table (transition table)

a tabular representation of the functional relationships among the present
states, inputs, next states and outputs of a sequential circuit.

Present state the current state of all the flip-flops at time, t.

Input (X) the value of X for each possible present state.
Next state the states of the flip-flops one clock cycle later at time t+1.
Output (Y) the value of Y at time t for each present state and input condition

In general, a state table can either be written as

or in a two (2) dimensional form as

state table (transition table)

The derivation of state table consists of first listing all possible binary combinations of
present states and inputs

For example, the state table for the 3-bit up/down binary counter that counts from the
binary states from 0 to 7 when X (user selection) is HIGH and counts from 7 to 0
when X is LOW is given as

Present state

Next state
X=0

X=1

Q2 Q1 Q0 Q2+ Q1+ Q0+ Q2+ Q1+ Q0+

0

Some common terms

Characteristics table a table that defines the next state as a function of
present state and inputs
Characteristic equation - a equation that specifies the next-state after a
clock pulse of the flip-flop as a function of the present states and inputs
before the clock pulse
Excitation table - the input value(s) required to obtain each possible next
state value after the clock pulse, given the present state value before the
clock pulse

Summary of flip-flop excitation tables

Example 1: Design of a 3 bit up-down synchronous

counter
Please change input X Y in Example 1a and 1b for consistency

Present state

Next state
Y=0

Q2 Q1

1. State diagram
The up-down selection by
the user is represented by a
variable Y

Y=1

Q0 Q2+ Q1+ Q0+ Q2+ Q1+ Q0+

2. State table

Example 1a: Design of a 3 bit up-down sync.

counter using J-K FF cont ...
3. Excitation table of a J-K flip-flop
Excitation Table

Q Q+ J

Example 1a: Design of a 3 bit up-down

synchronous counter using J-K FF cont ...
Present state

Next state
Y=0

Q2 Q1

Flip-flop inputs
Y=1

Q0 Q2+ Q1+ Q0+ Q2+ Q1+ Q0+

Y=0

Y=1

J2K2J1K1J0K0

J2K2J1K1J0K0

1X1X1X

0X0X1X

0X0XX1

0X1XX1

0XX11X

0XX01X

0XX0X1

1XX1X1

X11X1X

X00X1X

X00XX1

X01XX1

X0X11X

X0X01X

X0X0X1

X1X1X1

4. State table for a 3-bit up-down synchronous counter with J-K flip-flops

Example 1a: Design of a 3 bit up-down

synchronous counter using J-K FF cont ...

4. Karnaugh maps implementation to obtain the flip-flop input equations

Q0Y
00
Q2Q1
00
1

01

11

QY
10 Q Q 0 00
2 1
00 1
0

01

11

10

QY
10 Q Q 0 00
2 1
00 1
0

01

11

01

01

01

11

11

11

10

10

10

01

11

10

J2 = Q0Q1Y + Q0Q1Y
Q0Y
00
Q2Q1
00 X

J1 = Q0Y + Q0Y

J0 = 1

01

01

Q0Y
10 Q2Q1 00
00 X
X
01 X
0

11

11

11

10

10

10

01

11

QY
10 Q Q 0 00
2 1
00 X
X

K2 = Q0Q1Y + Q0Q1Y

01

11

K1 = Q0Y + Q0Y

K0 = 1

Example 1a: Design of a 3 bit up-down

synchronous counter using J-K FF cont ...
5. Flip-flop input equations

FF2

FF1

FF0

J2 = K2 = Q0Q1Y + Q0Q1Y

J1 = K1 = Q0Y + Q0Y

J0 = K0 = 1

6. Counter implementation

Example 1b: Design of a 3 bit up-down

synchronous counter using T FF cont ...
3. Excitation
table of a
T flip-flop
Excitation
Table

Q+

Example 1b: Design of a 3 bit up-down

synchronous counter using T FF cont ...
Present state

Next state
Y=0

Flip-flop inputs
Y=1

Y=0

Y=1

Q2 Q1 Q0 Q2+ Q1+ Q0+ Q2+ Q1+ Q0+ T2 T1 T0 T2 T1 T0

0

4. State table of 3-bit up-down synchronous counter with T flip-flop

Example 1b: Design of a 3 bit up-down

synchronous counter using T FF cont ...

Q0Y
Q2Q1 00
00 1

01
1

11
1

Q0Y
10 Q2Q1 00
1
00 1

01
0

11
1

QY
10 Q Q 0 00
2 1
00 1
0

01
0

11

10

01

01

01

11

11

11

10

10

10

T0 = 1

T1 = Q0Y + Q0Y

T2 = Q0Q1Y + Q0Q1Y

74HC190 up-down counter

Logic diagram for the 74HC190, an up/down synchronous decade counter.
The direction of the count is determined by the level of the up/down input.
When this input is HIGH, the counter counts down; when it is LOW, the
counter counts up.
This device can be preset to any desired BCD digit as determined by the
states of the data inputs when the LOAD input is LOW.
The MAX/MIN output produces a HIGH pulse when the terminal count nine
(1001) is reached in the UP mode or when the terminal count zero (0000) is
reached in the DOWN mode.
The MAX/MIN output, the ripple clock output , and the count enable input
are used when cascading counters.

Timing signal of 74HC190

Binary and gray code representation

Gray code
Gray code is an unweighted code
that has a single bit change between
one code word and the next in a
sequence. Gray code is used to
avoid problems in systems where an
error can occur if more than one bit
changes at a time.

Decimal

Binary

Gray code

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

Newly added

Example 2: Design of a 3 bit synchronous Gray

code counter
Gray code a binary numeral system where two successive values differ
in only one bit.
Design procedures:
Next state
2. State table Present state

1. State diagram

Q2

Q1

Q0 Q2+ Q1+ Q0+

Example 2: Design of a 3 bit synchronous Gray

code counter using J-K FF cont
3. Excitation table
of a J-K flip
flop
Excitation
Table

Q Q+ J

0 X

1 X

4. State table of 3-bit Gray code counter with J-K

flip-flops
Present
Next state
Flip-flop inputs
state
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0

Example 2: Design of a 3 bit synchronous Gray

code counter using J-K FF cont
5. Karnaugh maps to obtain the flip-flop input equations

Example 2: Design of a 3 bit synchronous Gray

code counter using J-K FF cont
5. Flip-flop input equations

FF2

FF1

FF0

J0 = Q2Q1 + Q2Q1

J1 = Q2Q0

J2 = Q1Q0

K0 = Q2Q1 + Q2Q1

K1 = Q2Q0

K2 = Q1Q0

6. Counter implementation

Unused states
In all the previous examples, all the three / four bit combinations were
used in the state assignment.
With p bits, the number of states, s, that can be coded is 2p-1 < s <= 2p
In general, when coding s states with p bits, some binary information are
not assigned to any state (unused states). Hence, the Karnaugh maps (Kmaps) constructed from the next-state table have no entries.
When a network is initially started, the network may enter one of the
unused states, for example, as a result of noise or some hardware failure.
self-correcting - the counter in which all the states are not included in the
original counting sequence eventually lead to the normal counting
sequence after one or more count pulses applied to the control input
To avoid a counter hanged-up, it should always be designed as selfcorrecting
There are two approaches to design networks with unused states i.e.:
replace the unused entries in K-maps with dont cares (X) (however,
the designed counter is not necessarily self-correcting) or
to ensure that the counter always go to a well-defined state, specify a
valid next-state entry for each of the unused state

Example 3: Design of a 3 bit arbitrary

sequence binary counter
Present state

1. State diagram
There are two unused states
i.e. 011 and 111

QA

QB

Next-state

QC QA+

QB+

QC+

2. Next-state table

dont cares

Example 3: Design of a 3 bit arbitrary

sequence counter
3. Excitation
table of a
D flip-flop
Excitation
Table

4. State table of 3-bit arbitrary sequence counter

with D flip-flops
Present state
QA

QB

Next-state

QC QA+

Flip-flop inputs

QB+

QC+

DA

DB

DC

The input values of

D flip-flops are the
same as the nextstate values

Example 3: Design of a 3 bit arbitrary

sequence counter using D FF cont
QAQB 4. Karnaugh maps
QC
00 01 11 10
0 0
1 0 1
1

0 X X 1
DA+ = QAQB + QAQB

QAQB
QC
00
0 0
1

QAQB
QC
00
0 1
1

01
0

11 10
0 0

X X
DB+ = QC

01 11 10
0 0 1
X

DC+ = QBQC

5. Counter implementation

Verify output for unused states

1. Determine
the flip-flop
input equations

2. Put the counter in the

unused state; then determine
the inputs for this state.

3. Use the new inputs

to determine the next
state:

Outputs

Flip-flop inputs

QA

QB

QC

4. Set up the next

group of inputs from
the current output.

Next state

DA =

DB =

DC =

QAQB+QAQB

QC

QBQC

QA+

QB+

QC+

The next state is the same as the flip flop inputs for D flipflops

Newly added

Example 3: Design of a 3 bit arbitrary

sequence counter using D FF cont
An analysis shows that if the counter, by accident, gets into one of the
invalid states (011 or 111), it will always return to a valid state according to
the following sequences: (011 110) and (111 010)
A complete state diagram of the arbitrary sequence counter including the
unused states are shown below

Example 3b: Design of a 3 bit arbitrary sequence

counter
Present state

1. State diagram
There are two unused states
i.e. 011 and 111

QA

QB

Next-state

QC QA+

QB+

QC+

2. Next-state table
Initialize the unused states with 000 state

Modulus of a counter
modulus of a counter number of unique states through which the counter will
sequence
maximum modulus the maximum possible of states of a counter is 2n, where n
is the number of flip-flops in the counter
truncated sequence the number of states with a sequence less than the
maximum of 2n
decade counter a counter with ten states in their sequence (MOD10). A
common modulus for counters
binary coded decimal (BCD) decade counter a decade counter with a count
sequence of zero (0000) through (1001). The ten-state sequence produce the
BDC code
to obtain a truncated sequence, it is necessary to force the counter to recycle
before going through all its possible states (e.g. a BCD counter must recycle back
to 0000 after 1001 state)

Example 4a: Design of a modulus 6

(MOD6) counter using T FF
Present state
QA QB

1. State diagram
The counter only uses SIX (6) out
of the EIGHT (8) available states.
States 110 and 111 are not used in
the design

Next-state

QC QA+ QB+ QC+

2. Next-state table
Dont cares (X)

Example 4a: Design of a modulus 6

(MOD6) counter using T FF cont
3. Excitation
table of a
T flip-flop
Excitation
Table

Q+

4. State table of a modulus 6 counter with T flip-flop

Present state
Next-state
Flip-flop inputs
QA QB QC QA+ QB+ QC+

TA

TB

TC

Example 4a: Design of a modulus 6 (MOD6)

counter using T FF cont
5. Karnaugh maps
QAQB
QAQB
QC
00 01 11 10
00 01 11 10 QC
0 0
0 X 0
0 0
0 X 0
1 1
1 X 0
1 0
1 X 1
TB+ = QAQC
TA+ = QAQC + QBQC
6. Counter implementation

QAQB
QC
00
0 1

01 11 10
1 X 1

1
1
TC+ = 1

If the counter gets into one of the invalid states

(110 or 111), it will always return to a valid
state according to the following sequences: (110
111 010)

Example 4b: Design of a modulus 6

(MOD6) counter using D FF cont
3. Excitation
table of a
D flip-flop
Excitation
Table

4. State table of a modulus 6 counter using D flip-flop

Present state
Next-state
Flip-flop inputs
QA QB QC

QA+ QB+ QC+

DA

DB

DC

Q Q+

Example 4b: Design of a modulus 6

(MOD6) counter using D FF cont
5. Karnaugh maps
QAQB
QC
00 01 11 10
0 0
0 X 1
1

0
1 X 0
DA+ = QAQC + QBQC

QAQB
QC
00
0 0
1

01 11 10
1 X 0

QAQB
QC
00
0 1

01 11 10
1 X 1

1 0
0 X
0 X 0
DC+ = QC
DB+ = QAQBQC + QBQC

6. Counter implementation

If the counter gets into one of the invalid

states (110 or 111), it will always return to
a valid state according to the following
sequences: (110 111 100)

Synchronous binary counter cont

An example of a 4 bit binary counter using
J-K flip-flops with a count enable input.
The first stage of A1 has its J = K = 1 if the
counter is enabled.
The other J and K inputs are equal to 1 if all
previous lower-order bits are equal to 1 and
the count is enabled.
The chain of AND gates generate the
required logic for the J and K inputs in each
stage.
The counter can be extended to any number
of stages, with each stage having an
additional flip-flop and an AND gate that
gives an output 1 if all previous flip-flops
outputs are 1.

Synchronous binary counter cont

An example of a 4 bit binary counter using D flip-flops with a count enable
input.
Equivalent circuit

Newly added red dashed box to show the circuit is equivalent

Binary counter with parallel load

Parallel loads for transferring an

initial binary number into the
counter prior to the count
operation.
An example of a binary counter
using J-K flip-flops with parallel
loads and the corresponding truth
table is given.

There was an error in the previous slide

Timing Diagram

Newly added

MOD 6 counter implementation using the

binary counter with parallel load
Q3 Q 2 Q 1 Q 0

Load input (synchronous input) - 0101

Both counter counts from 0000 to 0110.

Q3 Q 2 Q 1 Q 0

Clear input (asynchronous input) - 0110

Newly added

Binary counter with parallel load

This is another example of a
binary counter using D flipflops with parallel loads but
without an asynchronous clear
input

Ignore this slide

Asynchronous cascading
An example of a 2-bit and a 3-bit ripple counter connected in cascade. The
final output of the modulus-8 counter, Q4, occurs once for every 32 input
clock pulses. The overall modulus of the two cascaded counters is 4 8 =
32; that is, they act as a divide-by-32 counter.

Cascade: arrange (a
number of devices or
objects) in a series or
sequence

Synchronous cascading

The terminal count (TC) output of counter 1 is connected to the count enable
(CTEN) input of counter 2.
TC output of counter 1 goes HIGH when counter 1 completed the entire cycle
(when counter 1 reaches its terminal count).
This HIGH enables counter 2 that goes from its initial state to its 2 nd state.
Upon completion of the entire second cycle of counter 1 (when counter 1 reaches
terminal count the second time), counter 2 is again enabled and advances to its next
state. This sequence continues.
Since these are decade counters, counter 1 must go through ten complete cycles
before counter 2 completes its first cycle i.e., for every ten cycles of counter 1,
counter 2 goes through one cycle.
Thus, counter 2 will complete one cycle after one hundred clock pulses.
The overall modulus of these two cascaded counters is 10 10 = 100.

Synchronous cascading as frequency divider

Cascaded counters are often used to divide a high-frequency clock signal to
obtain highly accurate pulse frequencies. Known as countdown chains.
A basic clock frequency of 1 MHz signal is divided by 10, the output is 100
kHz. Then if the 100 kHz signal is divided by 10, the output is 10 kHz.
Another division by 10 produces the 1 kHz frequency. The general
implementation of this countdown chain is shown below

Cascaded counters with truncated sequences

a divide-by-40,000 counter (modulus 40,000) counter
The cascaded counter is preset to 25,536 (63C0 in hexadecimal) so that it
will count from 25,536 up to 65,535 on each cycle (40,000 states).
The RCO output of the right-most counter is inverted and applied to the input
of each 4-bit counter.
Each time the count reaches its terminal value of 65,535, which is
1111111111111111, RCO goes HIGH and causes the number on the parallel
data inputs (63C016) to be synchronously loaded into the counter with the
clock pulse.
With this technique any modulus can be achieved by synchronous loading of
the counter to the appropriate initial state on each cycle.

Counter decoding
To decode a binary state 6 (110) of a 3-bit binary counter, the outputs of Q2,
Q1, and Q0 are connected to the input of a AND gate.
A HIGH appears on the output of the decoding gate, indicating that the
counter is at state 6. This is called active-HIGH decoding.
Replacing the AND gate with a NAND gate provides active-LOW decoding.

Question: How do you connect the circuit to decode a binary state 5 and 0?

Counter applications
Digital clock
Automobile parking
Parallel-to-Serial Data Conversion (Multiplexing)

Digital clock

Digital clock cont

An example of a simplified logic diagram of a digital clock that displays
seconds, minutes, and hours.
A 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and
divided down to a 1 Hz pulse waveform by a divide-by-60 counter.
The divide-by-60 counter is formed by a divide-by-10 counter followed by a
divide-by-6 counter.
The seconds and minutes counts are also produced by divide-by-60 counters

Digital clock cont

A divide-by-60 counter
The counter counts from 0 to 59 and then recycle to 0
The divide-by-10 portion is formed with a synchronous decade counter
The divide-by-6 portion is formed with a decade counter with a truncated
sequence achieved by using the decoder count 6 to asynchronously clear the
counter.
The terminal count, 59, is also decoded to enable the next counter in the
chain.
**Q0 = LSB
**Q3 = MSB

Digital clock cont

The hours counter is formed with a
decade counter and a flip-flop.
The decade counter advances
through all of its states from 0 9
On a clock pulse that recycles the
counter from 9 back to 0, the flipflop goes to the SET state (J = 1, K
= 0) and illuminates a 1 on the
tens-of-hours display.
The total count is ten (the decade
counter is in the zero state and the
flip-flop is SET).
When the total hour count advances
to 12, the Q2 output of the decade
counter is HIGH, the flip-flop is
still SET, and thus the decode-12
gate output is LOW.

This activates the LOAD input of the

decade counter. On the next clock
pulse, the decade counter is preset to
0001 from the data inputs, and the
flip-flop is RESET (J = 0, K = 1).
This logic always causes the counter
to recycle from 12 back to 1.

Automobile parking
The use of an up/down counter to monitor the available spaces in a onehundred space parking garage and provide for an indication of a full
condition by illuminating a display sign and lowering a gate bar at the
entrance.
The system consists of optoelectronic sensors at the entrance and exit of the
garage, an up/down counter and associated circuitry, and an interface circuit
that uses the counter output to turn the FULL sign on or off as required and
lower or raise the gate bar at the entrance.

Up/down counter
Optoelectronic sensors

Automobile parking cont

The up/down counter is initially preset to 0 using the parallel data inputs
Each automobile entering the garage activates a light sensor that produces an
electrical pulse (positive pulse).
This electrical pulse SETs the S-R latch. The LOW on the output of the latch puts
the counter in the UP mode. Also, the electrical pulse goes through the NOR gate
and clocks the counter on the LOW-to-HIGH transition counter is increased by 1
When the one-hundredth automobile enters, the counter goes to its last state
(10010). The MAX/MIN output goes HIGH and activates the interface circuit which
lights the FULL sign and lowers the gate bar.
When an automobile exits, the optoelectronic sensor produces a positive pulse,
which RESETs the S-R latch and puts the counter in the DOWN mode counter is
decreased by 1
If the garage is full and an automobile leaves, the MAX/MIN output of the counter
goes LOW, turning off the FULL sign and raising the gate.

Multiplexer
Multiplexing conversion of the parallel data bits to serial data bits on the
single transmission line.
parallel data - a group of bits appearing simultaneously on parallel lines
serial data - a group of bits appearing on a single line in a time sequence
Parallel-to-serial conversion is generally accomplished using a counter to
provide a binary sequence for the data-select inputs of a data
selector/multiplexer.
An example of the Q outputs of the modulus-8 counter connected to the
data-select inputs of an 8-bit multiplexer.