Training Hireg Rev01

DANIEL
Know-How in Process Control
HiREG
Electrodes Regulator Training
DANIELI
AUTOMATION
Danieli Automation
Headquarters
Via B.Stringher, 4
33042 Buttrio (UD) Italy
Tel. (39) 0432.518111

Fax (39) 0432.673177
E-mail: sales@dca.it
HiREG Training program
Aim of the application

Power Supply layout
Measuring system
Current and Voltage Transformer
M.V. Interface Transformer table
Hardware connection to PLC
PLC Interface
Electrode Regulator: Position Control
Loop
Linearization and regulation
parameters
Counter pressure: pressure control
loop
Cold test
This document contains proprietary information of Danieli Automation S.p.A. not disclosable, not reproducible. All Rights Reserved
REGULATION PRINCIPLES
HiREG Aim of the application

Impedance
regulation:
Istantaneous control of the
arc length by hydraulic
electrodes position control
Standard PLC
Individual regulators for

each phase, with phase
balancing
Control Loop Regulation
Electrode saving
function
1. Overcurrent reaction.
TUNING PARAMETERS
Speed
2. Not conductive material

reaction
Logging and real time

trends for machine tuning
and performance
improvement
Z error
REGULATOR
Pos
INITIAL
CONTACT
LOGIC
V
I
Z measure
REACTOR POSITION
PRIMARY VOLTAGE
CURRENT VALUE
TAP CHANGER POSITION
SET-POINT
CALCULATION
Z set
HiREG Position Control Loop
Regulation Algorithm
Ki * I Ku * U = 0
Main Parameters:
PAR. I , PAR. U
Ki
Kiph
Ku
: inputs U, I parametering and limiting functions

: conversion table from primary current to secondary current
: function for the balancing of the phases
: table for the furnace working points
HIREG BLOCK DIAGRAM
HiREG - Automation Block Diagram
EAF
HiREG
HIREG HYDRAULIC
HiREG Hydraulic Overview

Lifting
Columns
Unlocking
Valves
Line Pressure
transducers
Regulation
Valves
Accumulators
Counter Pressure
Transducers
Counter Pressure
Regulation Valve
Inlet
Outlet
HiREG Valve system
Actuator: Valve Tech. Spec.
Signal command 10V

Digital Regulator 10000
HiREG Valve system
Actuator: Valve Electrical drawing
MV TYPICAL LAYOUT
HiREG Power Supply Layout
Transformer HV-MV
Breaker
P.F. Compensation
Series Reactor
Furnace transformer
Secondary system and Electrode
FIELD SIGNALS MEASURE
PT and CT connection
HiREG Measuring system
Voltage transformer PT (TV)
50Hz
Important: Avoid shortcircuit condition for PT (TV)
Adaptive Current transformer TA
5/5 A
Diris
Trafo connection Delta/Delta
Important :always verify short circuit condition for CT (TA)
Adaptive Current transformer TA

Trafo connection Star/Delta
5/5:3 A
Important :always verify short circuit condition for CT (TA)
Trafo connection Star-Delta/Delta
5/5:3 A
Important
:always
verify
shortS.p.A.
circuit
condition
for
CT (TA)
This document contains
proprietary information
of Danieli Automation
not disclosable,
not reproducible. All Rights
Reserved
HiREG Voltage and current transducer

RMS converter
Input 0:100V or 0:8A
AC
Output 0:10 V DC
Time response <
50ms
Precision < 0.5%
Cl.= 0.5
Supply 230 V 50Hz
or 110 V 60 Hz
HIREG ELECTROTECNIC
Main Principles
HiREG Electrical Parameters (1)
Base electrical circuit:
Base circular diagram
Real Circular Diagram

For each tap of the
reactor (if any), a circular
diagram can be produced
to represent the allowed
working area for the
furnace.
APPARENT POWER [MVA]
RATED POWER [MVA]
MAX. POWER [MVA]
POWER FACTOR [-]
LOAD CURVES [V]
ELECTRODES
CURRENT
[kA]
ARC LENGTH [mm]
Theory of Series Reactor

Profile
MV BUSBAR
P_fu+jQ_fu+jQ_react
P_fu/S_2 = 0,77-0,78
Power
Melting
Refining
SERIES REACTOR
Boring
P_fu+jQ_fu
P_fu/S_1 > 0,8
FURNACE
TRANSFORME
R
P_arc
I_arc)
(V_arc
S_1
P_arc
P_fu
EAF
2
S_
losses
Boring :
P.F.<0.75 Varc < 300400
Melting :
P.F. >0.75 max Power
Refining :
CC = 6
R.I. Arc coverage condition
HIREG HW INTERFACES
Fail safe logic
HiREG Hardware connection to PLC
HIREG INTERFACE SIGNALS
With main automation PLCs

EAF or LRF
HiREG PLC Interface (1)
HIREG_WC_REM
DATATOFURNACEPLC
dpcoupler
:64bytes
STRCT:
EREG_REM
DBW000
INTF_WS_WATCHDOG_RG
watchdog
IN
030000
Always
changing
00
DBX002.00
INTF_BS_GEN_FLT
Regulatorgenericalarm
BB
0>1
1=true
00
DBX002.01
INTF_BS_TRP_FLT
Regulatorhigherpriorityfailure
BB
0>1
1=true
00
DBX002.02
DBX002.03
DBX002.04
INTF_BS_BRK_OPN_CNS
furnacebreakeropenconsent
BB
0>1
1=true
00
DBX002.05
DBX002.06
INTF_BS_ARC_ON
FurnaceArcOn
BB
0>1
1=true
31
DBX002.07
DBX003.00
INTF_BS_ELS_LW_QTA
Electrodeshaveallreachedrequestedquota
BB
0>1
1=true
31
DBX003.01
DBX003.02
DBX003.03
DBX003.04
INTF_BS_EL_CUR_HIGH
Phase123cumulativehighcurrent
BB
0>1
1=true
00
DBX003.05
INTF_BS_EL_CUR_HHIG
Phase123cumulativehighhighcurrent
BB
0>1
1=true
00
DBX003.06
DBX003.07
DBX004.00
INTF_BS_EL1_LW_QTA
Electrode1hasreachedrequestedquota
BB
0>1
1=true
DBX004.01
INTF_BS_EL1_CUR_HIGH
Electrode1highcurrent
BB
0>1
1=true
00
DBX004.02
INTF_BS_EL1_CUR_HHIG
Electrode1highhighcurrent
BB
0>1
1=true
00
DBX004.03
INTF_BS_EL1_POS_FLT
Electrode1Encoderfault
BB
0>1
1=true
00
DBX004.04
INTF_BS_EL1_SP_ZERO
Electrode1speediszero
BB
0>1
1=true
00
DBX004.05
INTF_BS_EL1_HISP_VLV
Electrode1highspeedvalveopeningcommand
BB
0>1
1=true
33
DB 156
To Furnace PLC

To Furnace PLC
DB 156
DBX010.00
INTF_BS_RCT_BRK_CLS_ENA
B
Saturablereactor:furnacebreaker
closingenabled
BB
0>1
1=true
31
DBX010.01
DBX010.02
INFT_BS_RCT_CUR_REACH
Saturablereactortargetcurrentis
reached
BB
0>1
1=true
31
DBX010.03
DBX010.04
INTF_BS_RCT_CUR_ALR_HIG
H
Saturablereactorcurrentoverhigh
limitSTOPCONVERTER
BB
0>1
1=true
31
DBX010.05
INTF_BS_RCT_CUR_ALR_LOW
Saturablereactorcurrentunderlow
limitSTOPCONVERTER
BB
0>1
1=true
31
DBW012
INTF_WS_EL1_VLT_RG
electrode1_voltage
IN
01200
01200
00
DBW014
INTF_WS_EL1_CUR_RG
electrode1_current
IN
050.00
KA
05000
00
DBD016
INTF_WS_EL1_POS
electrode1actualabsoluteposition
FL
06000
mm
06000
33
DBW020
DBW042
INTF_WS_PRIM_VL
Primaryvoltage
IN
042.00
KV
042.00KV
00
DBW052
INTF_WS_RCT_CUR_REF
Saturablereactorcurrentreference
IN
01650.0
016500
31
DBW054
INTF_WS_RCT_CUR_LIM_HIG
H
Saturablereactorcurrenthighlimit
value
IN
01650.0
016500
31
DBW056
INTF_WS_RCT_CUR_LIM_LOW
Saturablereactorcurrentlowlimitvalue
IN
01650.0
016500
31
From Furnace PLC
DB 156
DBW100
INTF_WC_WATCHDOG_RG
watchdog
I
N
030
000
Always
changing
00
DBX102.0
0
INTF_BC_EL1_LIFT_RG
electrode1lifting(regulator)
B
B
0>1
1=true
00
DBX102.0
1
INTF_BC_EL1_LOWR_RG
electrode1lowering(regulator)
B
B
0>1
1=true
00
DBX102.0
2
INTF_BC_EL1_AUTO_RG
electrode1automatic(regulator)
B
B
0>1
1=true
00
DBX102.0
3
INTF_BC_EL1_UNL_RG
Electrode1unlocked(regulator)
B
B
0>1
1=true
00
DBX102.0
4
INTF_BC_EL1_HIGH_RG
electrode1inhighpos.(regulator)
B
B
0>1
1=true
00
DBX102.0
5
INTF_BC_EL1_LOW_RG
electrode1inlowpos.(regulator)
B
B
0>1
1=true
00
DBX102.0
6
INTF_BC_EL1_HSPD_RG
electrode1highspeed(regulator)
B
B
0>1
1=true
00
DBX102.0
7
DBX103.0
0
DBX103.0
1
DBX103.0
2
DBX103.0
3
DBX103.0
4

DB 156
From Furnace PLC
DBX108.00
INTF_BC_ARC_INT_CMD
furnacebreakerarcinterruption
(command)
B
B
0>1
1=true
00
DBX108.01
INTF_BC_BRK_CLS_STA
furnacebreakerclosed(status)
B
B
0>1
1=true
00
DBX108.02
INTF_BC_BRK_OPN_CMD
furnacebreakeropeningrequest(command)
B
B
0>1
1=true
00
DBX108.03
INTF_BC_CLAMPS
electrodesclampsmode
B
B
0>1
1=true
00
DBX108.04
INTF_BC_MAINT
Furnaceinmaintenancemode
B
B
0>1
1=true
00
DBX108.05
INTF_BC_HEAT_END
FurnaceHeatEnd
B
B
0>1
1=true
00
DBX108.06
INTF_BC_BCK_END
FurnaceBucketEnd
B
B
0>1
1=true
00
DBX110.00
INTF_BC_RCT_AUTO
Saturablereactorautomaticmode
B
B
0>1
1=true
31
DBX110.01
INTF_BC_RCT_RUN
Saturablereactorisrunning
B
B
0>1
1=true
31
DBX110.02
INTF_BC_RCT_BYP
Saturablereactorisbypassed
B
B
0>1
1=true
31

From Furnace PLC
DB 156
DBW112
INTF_WC_PRIM_VLT
primaryvoltage
IN
050.00
kV
05000
0
0
DBW114
DBW116
DBW118
INTF_WC_TAP_POS_RG
tapchangerposition
IN
132
132
0
0
DBW120
INTF_WC_CUR_SET_RG
currentcurveposition(SET)
IN
16
16
0
0
DBW122
INTF_WC_RCT_POS
reactorposition
IN
16
16
0
0
DBW124
INTF_WC_ACT_PWR
Activepower
IN
01000.0
MW
010000
0
0
DBW126
INTF_WC_RCT_PWR
Reactivepower
IN
01000.0
MVA
R
010000
0
0
DBW128
INTF_WC_COSPHY
Cosphy
IN
01.000
01000
0
0
DBW142
INTF_BC_RCT_CUR_TRG_MA
N
Saturablereactortargetcurrentin
manualmode
IN
01650.0
016500
3
1
DBW144
INTF_BC_RCT_CUR_ACT
Saturablereactorrealcurrent
IN
01650.0
016500
3
1
HIREG OWS
HiREG Communication Overview
HiREG Communication settings

DPI
CONFIGURATOR
HIREG OWS PARAMETERS
Reference document:
Admittance Table
HiREG Transformer Table (1)

Transformer Primary side connection
Important: Electrode line

current
CT Settings
KI-KA Automatic
calculation
HiREG Transformer Table (2)
KI
KA
HiREG Regulation Parameters
Regulation
Valve settings
Additional
Settings
V/I presence
PI Regulator
settings
Notch Filter
Settings
Touch Down
Settings
Electrode
Speed settings
Boring phase
Settings
HiREG Regulation Parameters
Phase Balance
PHASE 1
PHASE 2
PHASE 3
PHASE BALANCE
CURRENT
ARC LENGHT
PHASE BALANCE
0,9
CURRENT
1+
ARC LENGHT
PHASE BALANCE
0,9
0,9
CURRENT
1+ 1
1+ 2
(-1 + 2)
(-1 2)
(+1 2)
ARC LENGHT
HiREG Linearization (1)

SPEED RESPONSE CP=680 PSI
400
EL2
EL1
300
200
speed [mm/s]
Sequence:
1. Zero Valve
2. BIAS 1 mm/s
3. Linearization
EL3
100
0
-10000
-6000
-2000
-100
2000
6000
10000
reference [mV]
-200
-300
Automatic cycle
HiREG Regulation Parameters NLG

Gain increase in case of cave-in
Maintain symmetric
system response
HiREG Plant Parameters
Typical Measuring setting: pay attention to the correct value
HiREG Counter Pressure

Pressure control :
Counter pressure set ~80% Pb= Pcp Down Speed ~200mm/s (Pb: Pressure
balance)
Accumulator set ~65% Pcp
Backpressure
Backpressure
Trend
Set Points
Valve
Parameters
Alarms
Line pressure
Trends
Line Pressure
alarms
Switching
Settings
HiREG Communication settings

DB MidddleWare
Location
Dispatcher
settings
HiREG Reference documentation

Automation system technical specification - HiReg (o
HiReg Plus)
Functional Specification - HiReg (o HiReg Plus)
Operator manual HiReg OWS

Ac electric arc furnace - Furnace calculations - Working
points, circ.diagram, electrode reg.table
Commissioning manual

Training Hireg Rev01

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DANIEL

Know-How in Process Control

Tel. (39) 0432.518111

HiREG Training program

Aim of the application

HiREG Aim of the application

Individual regulators for

Control Loop Regulation

2. Not conductive material

Logging and real time

HiREG Position Control Loop

: inputs U, I parametering and limiting functions

HIREG BLOCK DIAGRAM

HiREG - Automation Block Diagram

HiREG Hydraulic Overview

HiREG Valve system

Actuator: Valve Tech. Spec.

Signal command 10V

HiREG Valve system

Actuator: Valve Electrical drawing

HiREG Power Supply Layout

FIELD SIGNALS MEASURE

HiREG Measuring system

Voltage transformer PT (TV)

Important: Avoid shortcircuit condition for PT (TV)

HiREG Measuring system

Adaptive Current transformer TA

HiREG Measuring system

Adaptive Current transformer TA

HiREG Measuring system

Trafo connection Star-Delta/Delta

HiREG Voltage and current transducer

HiREG Electrical Parameters (1)

Base electrical circuit:

Base circular diagram

HiREG Electrical Parameters (2)

Real Circular Diagram

HiREG Electrical Parameters (3)

Theory of Series Reactor

P_fu/S_1 > 0,8

P.F.<0.75 Varc < 300400

P.F. >0.75 max Power

R.I. Arc coverage condition

Fail safe logic

HiREG Hardware connection to PLC

HIREG INTERFACE SIGNALS

With main automation PLCs

HiREG PLC Interface (1)

HiREG PLC Interface (2)

HiREG PLC Interface (3)

From Furnace PLC

HiREG PLC Interface (4)

From Furnace PLC

HiREG PLC Interface (5)

HiREG Communication Overview

HiREG Communication settings

HIREG OWS PARAMETERS

HiREG Electrical Parameters (1)

HiREG Transformer Table (1)

Important: Electrode line

HiREG Transformer Table (2)

HiREG Regulation Parameters

HiREG Regulation Parameters