Analog to Digital Conversion

ADC Essentials
A/D Conversion Techniques
Interfacing the ADC to the IBM PC
DAS (Data Acquisition Systems)
How to select and use an ADC
A low cost DAS for the IBM PC

Why ADC ?

Digital Signal Processing is more popular

Easy to implement, modify,
Low cost

Data from real world are typically Analog

Needs conversion system
from raw measurements to digital data
Consists of

Amplifier, Filters
Sample and Hold Circuit, Multiplexer
ADC

Chap 0

ADC Essentials

Basic I/O Relationship

ADC is Rationing
System

x = Analog input /
Reference

n bits ADC
Number of discrete output
level : 2n
Quantum

LSB size
Q = LSB = FS / 2n

Quantization Error
1/2 LSB
Reduced by increasing n

Fraction: 0 ~ 1

Chap 0

Converter Errors

Chap 0

Offset Error

Gain Error

Can be eliminated by initial

adjustments

Integral Linearity Error

Differential Linearity Error

Nonlinear Error

Hard to remove

Terminologies

Chap 0

Converter Resolution
The smallest change
required in the analog
input of an ADC to change
its output code by one
level
Converter Accuracy
The difference between
the actual input voltage
and the full-scale weighted
equivalent of the binary
output code
Maximum sum of all
converter errors including
quantization error

Conversion Time
Required time (tc) before
the converter can provide
valid output data
Converter Throughput Rate
The number of times the
input signal can be
sampled maintaining full
accuracy
Inverse of the total time
required for one
successful conversion
Inverse of Conversion time
if No S/H(Sample and
Hold) circuit is used
5

More on Conversion Time

Input voltage change

during the conversion
process introduces an
undesirable uncertainty
Full conversion accuracy is
realized only if this
uncertainty is kept low
below the converters
resolution

Chap 0

Rate of Change x tc
resolution
dV
FS
(

dt

) max

2 n tc

Example
8-bit ADC
Conversion Time: 100sec
Sinusoidal input

vi of change
A sin(2
Rate

dvi
fA cos(2 ft ) 2 fA
Let FS=22A
dt
2 fA

ft )

2A
2 n tc

Limited ftoLow1frequency
of 12.4

12.4
Hz
Hz
2n t

Few Applications

S/H increase Performance

S/H (Sample and Hold)

Analog circuits that

quickly samples the
input signal on
command and then
holds it relatively
constant while the ADC
performs conversion
Aperture time (ta)

Chap 0

Example

20 nsec aperture time

1
62.17 KHz
n
2 ta

Reasonably good for

100sec converter

Time delay occurs in S/H

circuits between the time the
hold command is received and
the instant the actual transition
to the hold mode takes place
Typically, few nsec

Analog Input Signal

Typically, Differential or Singleended input signal of a single

polarity

Typical Input Range

Chap 0

Matching input signal

and input range

0 ~ 10V and 0 ~ 5V

If Actual input signal

does not span Full Input
range

Some of the converter output

code never used
Waste of converter dynamic
range
Greater relative effects of the
converter errors on output

Prescaling input signal

using OP Amp

In a final stage of
preconditioning circuit

By proportionally
scaling down the
reference signal

If reference signal is
adjustable

Converting bipolar to unipolar

Using unipolar converter when

input signal is bipolar

Scaling down the input

Adding an offset

Add
offset
scaled

Bipolar Converter

If polarity information in
output is desired
Bipolar input range

Typically, 0 ~ 5V

Bipolar Output

Chap 0

Input signal is scaled and an

offset is added

2s Complement
Offset Binary
Sign Magnitude

Outputs and Analog Reference Signal

I/O of typical ADC

Errors in reference signal

From

ADC output

Number of bits

8 and 12 bits are typical

10, 14, 16 bits also available

Typically natural binary

BCD (3 BCD)
For digital panel meter, and
digital multimeter

Cause

Initial Adjustment
Drift with time and
temperature
Gain error in Transfer
characteristics

To realize full accuracy of

ADC

Precise and stable

reference is crucial

Typically, precision IC
voltage reference is used
5ppm/C ~ 100ppm/C

Chap 0

10

Control Signals

Start

From CPU
Initiate the conversion
process
To CPU
Conversion is in
progress

Chap 0

BUSY / EOC

HBE / LBE

From CPU
To read Output word
after EOC

HBE
High Byte Enable

LBE
Low Byte Enable

0=Busy: In progress
1=EOC: End of
Conversion

11

A/D Conversion Techniques

Counter or Tracking ADC

Successive Approximation ADC

Dual Slop Integrating ADC

Voltage to Frequency ADC
Parallel or Flash ADC

Chap 0

Most Commonly Used

Fast Conversion

Software Implementation
Shaft Encoder
12

Counter Type ADC

Block diagram

Operation
Reset and Start Counter
DAC convert Digital output of
Counter to Analog signal
Compare Analog input and
Output of DAC

Vi < VDAC
Continue counting

Vi = VDAC
Stop counting

Digital Output = Output of

Counter
Disadvantage
Conversion time is varied

Waveform

Chap 0

2n Clock Period for Full Scale

input

13

Tracking Type ADC

Tracking or Servo Type

Using Up/Down
Counter to track input
signal continuously

For slow varying input

Chap 0

Can be used as S/H circuit

By stopping desired
instant
Digital Output
Long Hold Time
Disabling UP (Down)
control, Converter generate
Minimum (Maximum)
value reached by input
signal over a given period

14

Successive Approximation ADC

Chap 0

Most Commonly used in

medium to high speed
Converters
Based on approximating
the input signal with binary
code and then
successively revising this
approximation until best
approximation is achieved
SAR(Successive
Approximation Register)
holds the current binary
value

Block Diagram

15

Successive Approximation ADC

Circuit waveform

Conversion Time

Serial Output is easily

generated

Chap 0

Logic Flow

n clock for n-bit ADC

Fixed conversion time

Bit decision are made

in serial order

16

Dual Slope Integrating ADC

Chap 0

Operation
T1
Integrate 0 vi dt
t2
Reset and integrate
0 Vr dt
Thus T1vi ( AVG ) t2Vr
t2
v

V
i ( AVG )
r
T1
Applications
DPM(Digital Panel Meter),
DMM(Digital Multimeter),

Excellent Noise Rejection

High frequency noise
cancelled out by integration
Proper T1 eliminates line
noise
Easy to obtain good
resolution
Low Speed
If T1 = 60Hz, converter
throughput rate < 30
samples/s

17

Voltage to Frequency ADC

VFC (Voltage to Frequency

Converter)
Convert analog input
voltage to train of pulses
Counter
Generates Digital output
by counting pulses over a
fixed interval of time

Low Speed
Good Noise Immunity
High resolution

Applicable to remote data

sensing in noisy
environments

Chap 0

For slow varying signal

With long conversion
time

Digital transmission
over a long distance

18

Parallel or Flash ADC

Chap 0

Very High speed

conversion
Up to 100MHz for 8 bit
resolution
Video, Radar, Digital
Oscilloscope
Single Step Conversion
2n 1 comparator
Precision Resistive
Network
Encoder
Resolution is limited
Large number of
comparator in IC

Homework #5-1

.

19

Software Implementation

Implementation with
software using
microprocessor

Chap 0

Counting
Shifting
Inverting
Code Conversion

Limited Practical Use

Availability of Good
performance with very
reasonable Cost

20

Shaft Encoder

Chap 0

Elctromechanical ADC
Convert shaft angle to digital
output
Encoding
Optical or Magnetic Sensor
Applications
Machine tools, Industrial
robotics, Numerical control

Binary Encoder
Misalignment of mechanism
causes large error

Ex: 011 111 (180deg)

Gray Encoder
Misalignment causes 1 LSB
error

21

Interfacing the ADC to the IBM PC

Interface Operations
Most-recent-data Scheme

At end of conversion it
updates an output FIFO
Automatically start new
conversion
CPU read FIFO to
acquire most recent data

CPU initiate conversion

every time it needs new
data
CPU check EOC until
conversion is finished

Using CPU Interrupt

Start-and-wait Scheme

Chap 0

CPU initiate conversion

every time it needs new
data
CPU can proceed to do
other thing
ADC interrupt CPU when
conversion is complete
CPU goes to ISR

See Chapter 3, For more

information about 8259A

22

Interface Software

Memory Mapped Transfers

ADC is assigned in
Memory Space

MRD, MWR signal

MOV instruction

More complex decoding

logic
I/O Mapped Transfers
ADC is in I/O Space

Chap 0

IOR, IOW signal

IN, OUT instruction

DMA (Direct Memory Access)

CPU release system bus
by the request of DMA
DMA controller carried out
data transfer by generating
the required addresses and
control signals
The system bus control
reverts back to CPU when
data transfer is finished
DMA is useful
High Speed
High volume data transfer

Disk Drive interface

More Simple decoding

logic
23

Interface Hardware

Parallel Data Format

Three state output

buffer in ADC
To Interface ADC

Serial Data Format

CPU + Decoding logic

To generate Chip
Select signal
To generate Start
Signal
To Check EOC
signal

Chap 0

Asynchronous Serial
transmission to send
data over long distance
to a monitoring station

UART is commonly
used

Interfacing 10 or 12 bit
ADC

Transfer data in chunks

of 8 bits one after
another
24

DAS (Data Acquisition System)

Chap 0

DAS performs the

complete function of
converting the raw
outputs from one or
more sensors into
equivalent digital
signals usable for
further processing,
control, or displaying
applications

Applications

Simple monitoring of a
single analog variable
Control and Monitoring
of hundreds of
parameters in a nuclear
plant

25

Single Channel System

Transducer

Generate signal of low

amplitude, mixed with
undesirable noise

Amplifier, Filters

Amplify
Remove noise
Linearize

S/H (Sample and Hold)

Reduce uncertainty error
in the converted output
when input changes are
fast compared to the
conversion time
In Multi-channel system

Chap 0

To hold a sample from

one channel while
multiplexer proceed to
sample next one
Simultaneous sampling
of two signal

26

Sample and Hold Circuits

Care in selecting hold

capacitor Ch
Low Value

High Value

Chap 0

Reduces acquisition time

Increase Droop
Minimize Droop
Increase acquisition time

Choose capacitor to get a

best acquisition time
while keeping the droop
per conversion below 1
LSB
27

Commercially Available S/H

Chap 0

28

Multi-channel System

Analog multiplexer
and a ADC

Chap 0

Low cost

Local ADCs and digital

multiplexer

Higher sampling rate

29

How to select and use an ADC

Range of commercially
available ADCs

Guidelines for using

ADCs

Chap 0

Use the full input range

of the ADC
Use a good source of
reference signal
Look out for fast input
signal changes
Keep analog and digital
grounds separate
Minimize interference
and loading problem

30

Commercially available monolithic

ADCs

Chap 0

31

Commercially available hybrid ADCs

Chap 0

32

A low cost DAS for the IBM PC

Multi-channel system

Less than $100

ADC0816 from
National
Semiconductor
Constant, repetitive
rate

Chap 0

1000 samples/s

Generating clock
For starting ADC
conversion
For causing interrupt
Make a pulse stream from
TCLK with short pulses of
duration = x BCLK/4

TCLK from 8253

Timer/Counter
Wide pulse

33

ADC circuit for

PC prototype
board

SCSLCT
(Start Conversion SeLeCT)
: Latched trough port 30CH
SCSLCT = H
Selection of 30AH (/E10)
start conversion
SCSLCT = L
TCLK start conversion

INTSLCT
(INTerrupt SeLeCT)
: Latched trough port 30CH
INTSLCT = H
EOC cause IRQ2
INTSLCT = L
No Interrupt
CPU read Status register
(Port 309H) to check EOC
Chap 0

34

Status Register

Chap 0

For polling TCLK and

EOC signal
Port 309H (/E9)
Polling of EOC results
in a low level after the
data from ADC have
been read

35

Throughput rate calculation

4.77MHz / 8
= 596KHz

Chap 0

36

Accuracy Calculation

Chap 0

Better than 1% accuracy is ensured

Actual accuracy with smooth input signal at room
temperature will be better than 0.5%

37

Basic Program for Controlling ADC

Sampling rate < 200 samples/s

Because OUT and IN
instruction in Basic takes 5ms

Chap 0

38

C Programming for Controlling ADC

Chap 0

Sampling from ADC channel 1 at 5ms interval and sending each sampled data point to
the DAC

39

Homework #5-2

Prototype board C
program

Chap 0

Outp(CNTRL,5)
.

40