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Input signal
Sampling rate
Throughput
Resolution
Range
Gain
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Digital Number
Digital number used are all basically binary : that is, each bit or unit of information
has one of two possible states.
These state are :
off, false, or 1
on, true , or 0
It is also possible to represent the two logic state by two different levels of current ;
however, this is much less popular than using voltages .
Word
are groups of levels representing digital numbers; the levels may appear
simultaneously in paralel , on a bus or groups of gate inputs or outputs,
serially (or in time sequence) on a single line,
as a sequence of parallel bytes (i.e. byte serial) or nibbles (small bytes)
Unipolar
Code
Bipolar
Codes
2N
VOLTAGE
(10V FS)
ppm FS
% FS
dB FS
2-bit
2.5V
250.000
25
-12
4-bit
16
625mV
62.500
6.25
-24
6-bit
64
156mV
15.625
1.56
-36
8-bit
256
39.1mV
3.906
0.39
-48
10-bit
1.024
9.77mV (10mV)
977
0.098
-60
12-bit
4.096
2.44mV
244
0.024
-72
14-bit
16.384
610 V
61
0.0061
-84
16-bit
65.536
153 V
15
0.0015
-96
18-bit
262.144
38 V
0.0004
-108
20-bit
1.048.576
9.54 V (10 V)
0.001
-120
22-bit
4.194.304
2.38 V
0.24
0.000024
-132
24-bit
16.777.216
596nV*
0.06
0.000006
-144
1 LSB
FSR
2 1
n
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offset error,
gain error,
integral nonlinearity and
differential nonlinearity.
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Absolute Accuracy (Total) Error -ADCThe absolute accuracy or total error of an ADC as shown in Figure is the maximum
value of the difference between an analog value and the ideal midstep value.
It includes offset, gain, and integral linearity errors and also the quantization error in
the case of an ADC
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Sampling Theory
Prior to the actual analog-to-digital conversion, the analog signal usually
passes through some sort of signal conditioning circuitry which performs
such functions as amplification, attenuation, and filtering.
The lowpass/bandpass filter is required to remove unwanted signals
outside the bandwidth of interest and prevent aliasing.
There are two key concepts involved in the actual analog-to-digital and digitalto-analog conversion process:
Sampling Theory
The system shown in Figure is real-time system ; i.e., the signal to the ADC is
continuously sampled at a rate equal to fS, and the ADC presents a new sample to
the DSP at this rate.
In order to maintain real-time operation, the DSP must perform all its required
computation within the sampling interval, 1/fS, and present an output sample to
the DAC before arrival of the next sample from the ADC.
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Matlab Example - 1
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Matlab Example - 2
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Matlab Example - 3
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Matlab Example - 4
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Matlab Example - 5
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Procces Gain
In many applications,
the actual signal of interest occupies a smaller bandwidth, BW.
If digital filtering is used to filter out noise components outside the bandwidth
BW, then a correction factor (called process gain) must be included in the quation
to account for the resulting increase in SNR.
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Dynamic Range
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A t
SNRADC
RMS
1
2f RMS
Example :
Ana log input signal 250 MHz
SNR 50 dB
Maximum RMS jitter 2 ps
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N PM A
A M
fVCO
f REF
R
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The latch thus performs a track-and-hold function, allowing short input signals
to be detected and held for further processing.
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ADC Architectures
Flash Converters
Successive Aproximation ADCs
Pipelined ADCs
Integrating ADC
Sigma-Delta ADC
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Classification ADC
Most ADC applications today can be classified into four broad market segments:
(a)
(b)
(c)
(d)
data acquisition,
precision industrial measurement,
voiceband and audio, and
high speed (implying sampling rates greater than about 5 MSPS).
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Flash Converters
Flash analog-to-digital converters, also known as parallel ADCS, are the fastest way
to convert an analog signal to a digital signal.
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Architecture Detail
The reference voltage for each comparator is one least significant bit (LSB)
greater than the reference voltage for the comparator immediately below it.
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Successive-Approximation ADCs
The successive-approximation ADC is by far the most
popular architecture for data-acquisition
applications, especially when multiple channels
require input multiplexing.
Modern IC SAR ADCs are available in resolutions from 8
bits to 18 bits, with sampling rates up to several
MHz.
Output data is generally provided via a standard
serial interface (I2C or SPI), but some devices are
available with parallel outputs
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Operation Algorithm
In order to process rapidly changing signals, SAR ADCs have
an input sample-and-hold (SHA) to keep the signal constant
during the conversion cycle.
The conversion starts with the internal D/A converter (DAC)
set to midscale.
The comparator determines whether the SHA output is
greater or less than the DAC output, and the result (the
most-significant bit (MSB) of the conversion) is stored in the
successive-approximation register (SAR) as a 1 or a 0.
The DAC is then set either to 14 scale or 34 scale
(depending on the value of the MSB), and the comparator
makes the decision for the second bit of the conversion
The result (1 or 0) is stored in the register, and the process
continues until all of the bit values have been determined.
At the end of the conversion process, a logic signal (EOC,
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DRDY, BUSY, etc.) is asserted.
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Pipelined architecture
In order to increase the speed of the basic subranging ADC, the pipelined
architecture has become very popular.
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- ADC architecture
Modern - ADCs for applications requiring high resolution (16 bits to 24 bits)
and effective sampling rates up to a few hundred hertz.
High resolution, together with on-chip programmable-gain amplifiers (PGAs),
allows the small output voltages of sensors such as weigh scales and
thermocouples to be digitized directly.
Proper selection of sampling rate and digital filter bandwidth also yields excellent
rejection of 50-Hz and 60-Hz power-line frequencies.
- ADCs offer an attractive alternative to traditional approaches using an
instrumentation amplifier (in-amp) and a SAR ADC.
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The heart of this basic modulator is a 1-bit ADC (comparator) and a 1-bit DAC (switch).
The output of the modulator is a 1-bit stream of data.
The noise-shaping function by acting as a low-pass filter for the signal and a highpass filter for the quantization noise.
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Example:
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Second-order - modulator
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24-bit - Converter
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s to 100 s.
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Example:
A 16-bit, 1-MSPS sampling ADC requires a serial output data rate of at least 16
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MHz, which would not be a problem with most modern P, Cor DSPs.
Example:
Using a maximum LVDS serial data link of 600 Mbits/s requires parallel data
transmission for resolutions/sampling rates greater than 8 bits at 75 MSPS, 10
bits at 60 MSPS, 12 bits at 50 MSPS, 14 bits at 43 MSPS, 16 bits at 38 MSPS,88
etc.
Example:
Voltage references have a major impact on the performance and accuracy of
analog systems. A 5-mV tolerance on a 5-V reference corresponds to 0.1%
absolute accuracyonly 10 bits. For a 12-bit system, choosing a reference that
has a 1-mV tolerance may be far more cost effective than performing manual
calibration, while both high initial accuracy and calibration will be necessary in a
system making absolute 16-bit measurements.
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Ratiometric
ADC can be driven from a single supply voltage which is also used to excite the
remote bridge. Both the analog input and the reference input to the ADC are high
impedance and fully differential. By using the + and SENSE outputs from the
bridge as the differential reference to the ADC, the reference voltage is proportional
to the excitation voltage which is also proportional to the bridge output voltage.
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Primary
What is the required level of system accuracy?
How many bits of resolution are required?
What is the nature of the analog input signal?
How fast must the converter operate (conversion speed)?
What are the environmental conditions?
Is a track-and-hold circuit required?
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Caracteristics ADC
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