Integrated

Circuits

Presented by: Guillermo Castillo

What is a 3D IC??
3D Integrated
circuit is a chip
which
accommodates two
or more layers of
active electronic
components
They are
integrated both
horizontally and
vertically onto a
single circuit.

2D Integrated Circuits
Moores Law
Gordon Moore establish a
prediction that later became
the famous Moores Law.
The simplified version of this
law states that processor
speeds, or overall processing
power for computers will
double every two years.

Limitation of 2D Integrated
Circuits Moores Law
But, the physical limitations of the materials used for ICs are almost
deconstructing Moores Law.

Manufacturing costs
Energy consumption
Physical space
the limits of lithography
(process of printing)
the transistor size is
reaching its limit (Actually
14 nanometers)
Algorithms (Instructions)

Limitation of 2D Integrated
Circuits Moores Law

While chips may still shrink and become

more powerful, although at a slower rate,
the technological deflation may be slowin

Essentially, the next iteration of Moores

Law will require a more expensive
basket of technologies. Already, the
transistors are smaller than the wave
length of light used to print the chips.

Why Move From 2D to 3D ICs?

Demand of Very-large-scale
integration (VLSI) circuits with
features
Higher operating frequencies
Data transfer rate
Increment in functionality
Less power consumption
Coming limitations of 2D
Integrated circuits
Development and
manufacturing costs
Lack of physical space and
others

VLS
I

Why 3D?

Reduction of chip area

Chip stacking brings neighboring circuits
closer by making connection in third
dimension. As a result the chip area
decreases.
Performance and energy efficiency
Energy dissipation decreases with the
number of layers used in the design
3D ICs reduces wire length, thus cutting
down wire, delays and power.
Percentage of Reduction
Reducing interconnect length in designs
can dramatically reduce RC delays and
increase chip performance

Why 3D?

Why 3D?

A scalable solution to multiple

core-on-chip design
Future will see more than 80 cores
in a single chip that needs better
communication strategy (Intel)
Improving interconnections among
different wafers*.
Can be used to accommodate
both homogenous and
heterogeneous chips.
Complete systems on chip
(Heterogeneous)
3D Processors
80 Cores processor
(Homogeneous)
(Intels Teraflops Research Chip)
Reduction of unutilized space on
the substrate.

* Wafers: Thin slice ofsemiconductor material, such as acrystalline silicon, used in electronicsfor thefabricationofintegrated circ

Why 3D?

3D Processor (Homogeneous)

Heterogeneous 3D IC

3D Integrated Circuits Promises

Timing
Data transfer time from one
transistor to another will be reduce
due the wiring length reduction
Smaller timing delays will help to
achieve Higher frequencies

Delay Reduction
2 Layers 37% of reduction
3 Layers 57% of reduction
4 or 5 layers 65% of reduction

3D Integrated Circuits Promises

Metal Wire Connection

Reduction of 28% and above

Length of connections will be

reduce
Shorter metal wire connection
will reduce timing and power
consumption

3D Integrated Circuits Promises

Chip Reduction & Energy Consumption
50% of size reduction

Size of Silicon Chip

Energy Reduction
2 Layer 30%
3 Layer 35%
4 o 5 Layer 40%

Coming 3D Manufacturing
Technologies
Many options will be available for realization of 3D circuits
Choice of Fabrication will depends on requirements of Circuit System
Beam
Recrystallization
Deposit polysilicon and
fabricate TFTs*

-Not practical yet for

3D circuits due to high
temp of melting
polysilicon, because
suffers from Low
carrier mobility
-However high
performance TFTs
have been fabricated
using low temp
processing which can
be used to implement
3D circuits

Processed Wafer
Bonding

Silicon Epitaxial
Growth

Solid Phase
Crystallization

Bond two fully

Epitaxial grow a single
Low Temp alternative
processed wafers
crystal Silicon
to SE**
together

- High temperatures
- Offers Flexibility of
- Similar Electrical
cause significant
creating multiple layers
Properties on all
degradation in quality
- Compatible with
devices
of devices on lower
current processing
- Independent of
layers
environments
temperature since all
- Process not
- Useful for Stacked
chips are fabricated
manufacturable yet
SRAM and EEPROM
then bonded
cells
- Good for applications
where chips do
independent
processing
- However Lack of
Precision (alignment)
restricts interchip
* Thin Film Transistor
to
**Stirling engineis aheat communication
enginethat operates
by cyclic compression and expansion of air or other gas
global metal lines.

Concerns About 3D circuits

Thermal Issues in 3D-circuits

Due to reduction in chip size of a 3D implementation, 3D circuits

exhibit a sharp increase in power density
Analysis of Thermal problems in 3D is necessary to evaluate
thermal robustness of different 3D technology and design
options.

Electromagnetic interference
Interconnect Coupling Capacitance and cross talk
Coupling between the top layer metal of the first active layer and the device on
the second active layer devices is expected

Interconnect Inductance Effects

Shorter wire lengths help reduce the inductance
Presence of second substrate close to global wires might help lower inductance
by providing shorter return paths

Concerns About 3D
circuits
Reliability Issues
Electro thermal and Thermo-mechanical effects between
various active layers can influence electro-migration and chip
performance
Layer yield issues may arise due to mismatches between die
yields of different layers, which affect net yield of 3D chips.

Conclusions
The 3D Integrated circuits are a great relief to
interconnected IC technologies.
This opens up a new era in chip designing which has
many aspects still to be explored and exploited.
These can be used in many facets of our lives like
smartphones, microprocessor, based memory stacks,
etc.