HIERARCHICAL DESIGN

METHODOLOGY
IN FPGA
PRESENTED BY
P.NAVEEN SAI (15937)
M.LEELA MUKUND (15938)
S.SHASHIKANTH REDDY (16179)

contents
Introduction
Why hierarchical design methodology?
Solution
Pros and cons
Companies that implements this methodology
References

INTRODUCTION
Hierarchical design(HD) is an advanced design methodology implemented

on complex FPGAs

HD addresses the problems of long implementation runs

The designer can break up the design into smaller logical blocks
East block operates independently

WHY HIERARCHICAL DESIGN

METHODOLOGY ?
To achieve potential physical implementation problems prior to place and

route

Using this methodology it is no longer necessary to run place and route on

the entire flatten design , each time the designer makes a small change

With flat methodologies it is common to kickof

Multiple routing runs
Random seed values

continued..

 This method produces acceptable timing results

It reduces number of back end iterations
It is stable

SOLUTION
A floor planning is created and proper analysis is done

This interconnecting methodology implements one acceptable timing route

Improves performance

continued.

 proper integrated floor planning fixes

Timing knots
Long critical paths
Complex clocking schemes
High fan out
Controlling the utilization of desired space is seen in this methodology

Controlling utilization
It is an important aspect of FPGA design
Volume production plays a vital role here
It is much easier through block level techniques of a hierarchical design

methodology

Some designers leave ample amount of space while designing the FPGA for

upgrades.

INTELLECTUAL PROPERTY(IP) FLOW

Designers can split their work into smaller, more manageable, block-based

pieces, these blocks are called IP blocks

IP blocks can be reused from previous designs

Designers can freeze the placement within these blocks so that timing,

power, and other physical characteristics are fixed and known to meet their
requirements

Designers will quickly connect these blocks to form larger, more complex

designs that meet their physical requirements

Each component of logic block of the FPGA design meets their timing

requirements.

THE NEW FPGA DESIGN

PARADIGM

PROS:
Improves design performance
Shortens connectivity lengths
Timing problems can be identified earlier
Adjustments can be made without interrupting the design
Timing analysis results are in minutes instead of waiting for hours

CONS:
Needs more design resourses for the design and place and route on

multiple blocks

Need to budget the timing and clock trees on each level of block
Sometimes a tool may not be able to handle a large chip in a flat level

COMPANIES THAT IMPLEMENTS THIS

METHODOLOGY
Xilinx Inc
Altera
Intevac

REFERENCES
www.eetimes.com
www.xilinx.com
www.altera.com