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METHODOLOGY
IN FPGA
PRESENTED BY
P.NAVEEN SAI (15937)
M.LEELA MUKUND (15938)
S.SHASHIKANTH REDDY (16179)
contents
Introduction
Why hierarchical design methodology?
Solution
Pros and cons
Companies that implements this methodology
References
INTRODUCTION
Hierarchical design(HD) is an advanced design methodology implemented
on complex FPGAs
route
the entire flatten design , each time the designer makes a small change
continued..
SOLUTION
A floor planning is created and proper analysis is done
continued.
Controlling utilization
It is an important aspect of FPGA design
Volume production plays a vital role here
It is much easier through block level techniques of a hierarchical design
methodology
Some designers leave ample amount of space while designing the FPGA for
upgrades.
power, and other physical characteristics are fixed and known to meet their
requirements
Designers will quickly connect these blocks to form larger, more complex
Each component of logic block of the FPGA design meets their timing
requirements.
PROS:
Improves design performance
Shortens connectivity lengths
Timing problems can be identified earlier
Adjustments can be made without interrupting the design
Timing analysis results are in minutes instead of waiting for hours
CONS:
Needs more design resourses for the design and place and route on
multiple blocks
Need to budget the timing and clock trees on each level of block
Sometimes a tool may not be able to handle a large chip in a flat level
REFERENCES
www.eetimes.com
www.xilinx.com
www.altera.com