|



  
Course contents

Digital
‡ Digital design
design
‡ Combinatorial circuits: without status
Combina-
torial
‡ Sequential circuits: with status
circuits
‡ FSMD design: hardwired processors
Sequential
circuits
˜ Language based HW design: VHDL
FSMD
design

VHDL

5/1
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/2
|



  
Language based HW design:
a VHDL primer
Digital
˜ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/3
|



  
VHDL primer: Introduction

Digital
‡ Acronym:
design
˜ VHDL = VHSIC Hardware Description Language
Combina- ˜ VHSIC = Very High Speed Integrated Circuit
torial
circuits ‡ What is VHDL?
˜ A programming language for describing the behavior
Sequential
circuits of digital systems
˜ Design entry language, used for
FSMD
design ˜ Unambiguous specification at behavioral and RTL
level
VHDL ˜ Simulation (executable specification«)
˜ Synthesis
˜ Documentation
‡ Standardisation: IEEE 1076
˜ First version: 1986
˜ Second version: 1993
˜ New version about to appear
5/4
|



  
VHDL primer: Introduction

Digital
‡ When to use VHDL instead of schematics?
design
˜ Drawbacks:
Combina- ˜ VHDL is easy to learn but hard to master
torial (semantics are quite different from software
circuits
languages)
Sequential ˜ VHDL has a difficult syntax (Language sensitive
circuits editors with templates for all language
constructs)
FSMD
design ˜ VHDL is very ¶wordy·: lots of code to type for just
a few simple things
VHDL ˜ A list of instructions is less intuitive to
understand than a block diagram for a human
being
˜ VHDL is designed to make simulation efficient:
contains aspects that have hardly anything to do
with hardware behavior, but is useful to speed-up
event driven simulation

5/5
|



  
VHDL primer: Introduction

Digital
‡ When to use VHDL instead of schematics?
design
˜ Easier to capture complex circuits: higher level
Combina-
of abstraction with automated synthesis
torial
circuits ˜ you specify ¶add· instead of jotting
down a specific type of adder: the
Sequential
circuits synthesis tool will instantiate the
FSMD
best type of adder under timing, area
design & power constraints
VHDL ˜ easy to parametrise (e.g. word
length, queue depth)
˜ easy to specify arrays of components
˜ Portable across many tools for simulation,
synthesis, analysis, verification, « of different
vendors (e.g. Synopsys, Mentor Graphics, «)

5/6
|



  
VHDL primer: Introduction

Digital
‡ Limitations of VHDL
design
˜ The standard only describes syntax and
Combina-
semantics, but not the coding style
torial ˜ you can specify the same behavior (e.g. MUX) in
circuits
an almost unlimited number of ways
Sequential ˜ each leading to a completely different
circuits implementation (e.g. Multiplexor or tri-state bus)
˜ which is synthesis tool dependent.
FSMD
design ˜ You should do lots of experimentation with style-
tool combinations to be able to predict how the
VHDL hardware will look like that will be synthesised.
Is prediction necessary? You also do not predict
the ASM generated by C; C is less efficient than
ASM but faster to write. Currently, it is hard to
tolerate the inefficiency caused by the higher
level specification for hardware.
˜ Note: for DSP processors programmed in C, we do
predict ASM and have to experiment with style-
5/7 compiler combinations for efficiency reasons!!
|



  
VHDL primer: Introduction

Digital
‡ Limitations of VHDL (ctud)
design
˜ ¦nly a subset of VHDL can be automatically
Combina-
synthesised; each vendor supports a different
torial subset
circuits
˜ ¦nly digital; special extension (not yet widely
Sequential adopted) for analog: VHDL-AMS (acronym for
circuits
VHDL Analog and Mixed Signal)
FSMD
design
˜ IEEE standard 1076.1-1999
˜ is a super-set of the full IEEE VHDL
VHDL
1076-1993 standard for digital design

5/8
|



  
VHDL primer: Introduction

Digital
‡ Abstraction levels
design
˜ ½ehavioral
Combina- ˜ Interconnected functions
torial
circuits
˜ ¦nly info on functions or algorithms
Sequential (what)
circuits
˜ ¦nly timing needed to let the
FSMD
design
function work correctly
˜ ¦ for VHDL
VHDL
˜ ½ehavioral synthesisers immature;
used for high level executable
specification in top-down design and
manual synthesis into RTL

5/9
|



  
VHDL primer: Introduction

Digital
‡ Abstraction levels
design
˜ RTL
Combina- ˜ Interconnected registers and combinatorial units
torial
circuits
˜ Info on function (what) and architecture (how)
˜ Cycle accurate
Sequential ˜ No technology dependent timing info
circuits
˜ ¦ for VHDL
FSMD ˜ Good synthesisers
design
˜ Gate level
VHDL ˜ Interconnected gates and flip-flops
˜ Info on function and architecture
˜ Info on technology dependent timing (gate
delays)
˜ Layout
˜ Info on layout on silicon
˜ Continuous timing
5/10 ˜ Analog effects
|



  
VHDL primer: Introduction

Digital
‡ ¦ther hardware description languages
design
(HDL)
Combina- ˜ Verilog
torial
circuits ˜ More widespread in USA than in
Sequential
Europe
circuits
˜ ¦ften required for gate level or RTL
FSMD level ASIC sign-off
design
˜ Never ending discussion which is
VHDL
better
˜ PLD languages like A½EL, PALASM, «
˜ These are more at the gate level,
capturing also technology dependent
features (e.g. detailed timing)

5/11
|



  
VHDL primer: Introduction

Digital
‡ Difference between HDLs and traditional
design
software programming languages
Combina- ˜ Concurrency: all hardware components operate
torial
circuits
in parallel
˜ Data types: support is needed for arbitrary size
Sequential
circuits
integers, bit vectors, fixed point numbers
˜ Concept of time
FSMD
design

VHDL

5/12
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
˜ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/13
|



  
A First look at VHDL:
Example 1 task description
Digital
‡ Design a circuit named ¶Test· with 3 8-bit
design
inputs (In1, In2, In3) and two boolean
Combina- outputs (¦ut1, ¦ut2). The first output
torial
circuits equals ¶1· when the first and second input
are equal; the second output equals ¶1·
Sequential
circuits when the first and third input are equal.
FSMD ‡ Let·s first make a schematic design:
design

VHDL

5/14
|



  
A First look at VHDL:
Schematic specification
Digital
‡ The circuit will be hierarchically
design
decomposed into a top level component
Combina- ¶Test· containing 2 instantiations of a
torial
circuits comparator component ¶Compare·
Sequential
circuits Test
Compare
FSMD
In1 ¦ut1
design A
EQ
VHDL
½
In2
Compare
A
In3 EQ ¦ut2
½

5/15
|



  
A First look at VHDL:
Schematic specification
Digital
‡ The comparator is then hierarchically
design
decomposed into a gate level
Combina- combinatorial circuit
torial
circuits
Compare
Sequential
circuits A[0] XN¦R
A
FSMD ½[0]
design

A[1] AND
VHDL EQ
½[1] EQ

½
A[7]
½[7]

5/16
|



  
A First look at VHDL:
Entity and Architecture
Digital
‡ Declaration of the ¶Compare· design
design
entity: ¶Entity· specifies
Combina-
the interface
torial -- Eight bit comparator to the circuit, the
circuits -- black box of a
entity Compare is schematic
Sequential port( A,½: in bit_vector(0 to 7);
circuits EQ: out bit); Input and output
end entity Compare; signals are called
FSMD ¶ports·
design
architecture ½ehav1 of Compare is
begin ¶Architecture· describes
VHDL EQ <= ¶1· when (A=½) else ¶0·; the behavior and structure
end architecture ½ehav1; of the entity,
Notes: the internals of the box
- Multiple architectures per entity are possible: different ways
of implementing same behavior
- This architecture specifies behavior at RTL level and not
the actual structure of gates; synthesis tool will automatically
translate this RTL behavioral description into gate level
5/17 - Ports have an explicit direction and are (vectors of) bits
|



  
A First look at VHDL:
Component and Instantiation
Digital
‡ Specification of the next higher level in
design
the circuit hierarchy: ¶Test·
Virtual device: allows
-- Dual comparator Test component
Combina- for concurrent
torial
--
development of both
circuits entity Test is
hierarchical levels,
port( In1,In2,In3: in bit_vector(0 to 7);
by different persons.
Sequential ¦ut1,¦ut2: out bit);
¶Comparator· will be
circuits end entity Test;
bound to ¶Compare·
later
FSMD architecture Struct1 of Test is
design component Comparator is
port( X,Y: in bit_vector(0 to 7); Two instantiations
VHDL Z: out bit); of the same component
end component Comparator; ¶Comparator· with its
begin signal binding
Compare1: component Comparator port map (In1,In2,¦ut1);
Compare2: component Comparator port map (In1,In3,¦ut2);
end architecture Struct1;
Notes:
- The two ¶comparator· components work concurrently!!!
- This architecture describes structure, i.e. how this entity
5/18 consists of an interconnection of lower level components
|



  
A First look at VHDL:
Comparison with C
Digital
‡ This is very similar to software
design
programming languages, e.g. C
Combina-
torial /* Eight bit comparator
circuits */ Interface to the function
int Compare
Sequential (int A, int ½)
circuits
Inputs and outputs are
called ¶arguments·
{
FSMD
design
return (A == ½); ½ehavior of the function
}
VHDL

Notes:
- ¦nly one behavior per function possible
- ½ehavior is specified at rather high level and will be
automatically translated by the compiler into ASM instructions
- Function arguments do not have a direction and are of type int

5/19
|



  
A First look at VHDL:
Comparison with C
Digital
‡ This is how the higher hierarchical level
design
looks like in C
Combina- /* Dual comparator Test program
torial */
circuits

main()
Sequential {
circuits
Two calls to the function
int In1, In2, In3; ¶Compare· with its
int ¦ut1, ¦ut2; argument binding
FSMD
design
¦ut1 = Compare(In1, In2);
VHDL
¦ut2 = Compare(In1, In3);
}

Notes:
- The two ¶compare· function calls are executed sequentially
- This main program is executed once and stops. In VHDL, all
components describe relations that are valid continuously and
forever
5/20
|



  
A First look at VHDL:
Configuration
Digital
‡ When an entity has multiple
design
architectures, how do you indicate which
Combina- one to use?
torial
circuits ‡ How do you bind ¶Components· to
Sequential
¶Entities·?
circuits -- Configuration information: architecture selection
-- and component-entity binding
FSMD
½oth ¶use entity·s could
design be combined in one:
configuration ½uild1 of Test is
for All: Comparator ...
for Struct1
VHDL
for Compare1: Comparator use entity Compare(½ehav1)
port map (A => X, ½ => Y, EQ => Z);
end for;
for others: Comparator use entity Compare(½ehav1)
port map (A => X, ½ => Y, EQ => Z);
end for;
end for;
end configuration ½uild1;

5/21
Note: ¶configuration· corresponds in SW to ¶linking·
|



  
A First look at VHDL:
Syntax
Digital
design
ENTITY:
Combina-
torial entity Entity_name is
circuits
port( Signal_name: in Signal_type;
Signal_name: out Signal_type);
Sequential
circuits
end entity Entity_name;

FSMD
design

ARCHITECTURE:
VHDL

architecture Architecture_name of Entity_name is

local_signal_declarations;
component_declarations;
begin
statements;
end architecture Architecture_name;

5/22
|



  
A First look at VHDL:
Syntax
Digital C¦MP¦NENT:
design component Component_name is
port( Signal_name: in Signal_type;
Combina- Signal_name: out Signal_type);
torial end component Component_name;
circuits

Sequential C¦MP¦NENT INSTANTIATI¦N:

circuits -- component instantiation
Instance_name: component Component_name
FSMD port map (Signal_list);
design or
-- direct instantiation
VHDL Instance_name: entity Entity_name(Architecture_name)
port map (Signal_list);

Name used in
SIGNAL LIST: component declaration
-- two variants:
-- variant 1: ordered list of signals as in software languages
-- e.g. (In1,In2,¦ut1)
-- variant 2: named list Locally used name
-- e.g. (½ => In2, EQ => ¦ut1, A => In1)
5/23
|



  
A First look at VHDL:
Syntax
Digital
design C¦NFIGURATI¦N:

Combina- configuration Config_name of Entity_name is

torial for Architecture_name
circuits
for Instance_name: Component_name use entity
Entity_name(Architecture_name)
Sequential
circuits
port map (Signal_list);
end for;
end for;
FSMD
design end configuration Config_name;

VHDL

5/24
|



  
A First look at VHDL:
Example 2
Digital
‡ Declare a 3-input AND gate
design

Combina- A
Y
torial ½
circuits
C

Sequential
circuits
-- 3-input AND gate

entity AND3 is
FSMD
design port ( A,½,C: in bit;
Y: out bit);
VHDL
end entity AND3;

architecture RTL of AND3 is

begin
Y <= ¶1· when ((A=¶1·) and (½=¶1·) and (C=¶1·)) else ¶0·;
end architecture RTL;

5/25
|



  
A First look at VHDL:
Example 2
Digital
‡ Declare a 3-input ¦R gate
design

Combina- A
Y
torial ½
circuits
C

Sequential
circuits
-- 3-input ¦R gate

entity ¦R3 is
FSMD
design port ( A,½,C: in bit;
Y: out bit);
VHDL
end entity ¦R3;

architecture RTL of ¦R3 is

begin
Y <= ¶0· when ((A=¶0·) and (½=¶0·) and (C=¶0·)) else ¶1·;
end architecture RTL;

5/26
|



  
A First look at VHDL:
Example 2
Digital
‡ Declare an INV gate
design

Combina-
torial A Y
circuits

Sequential
circuits
-- INV gate

entity INV is
FSMD
design port ( A: in bit;
Y: out bit);
VHDL
end entity INV;

architecture RTL of INV is

begin
Y <= ¶1· when (A=¶0·) else ¶0·;
end architecture RTL;

5/27
|



  
A First look at VHDL:
Example 3
Digital
‡ ½uild a 2-to-1 MUX using both a
design
behavioral as well as a structural
Combina- description
torial A
circuits Y
½
Sequential
circuits S
entity MUX21 is The black box
port ( A,½,S: in bit; interface
FSMD
design Y: out bit);
end entity MUX21;
VHDL

architecture ½ehav of MUX21 is

begin ½ehavioral description
Y <= A when (S=¶1·) else ½;
end architecture ½ehav;

5/28
|



  
A First look at VHDL:
Example 3
Digital
‡ ½uild a 2-to-1 MUX using both a behav. as
design
well as a structural description A
Y
Combina- architecture Struct of MUX21 is ½
torial signal U,V,W : bit;
circuits component AND2 is S
port ( X,Y: in bit;
Sequential Z: out bit); Structural description
circuits
end component AND2;
component ¦R2 is A
FSMD
port ( X,Y: in bit; W
design
Z: out bit);
S Y
end component ¦R2;
VHDL
component INV is U V
port ( X: in bit;
Z: out bit); ½
end component INV;
begin
Gate1: component INV port map (X=>S,Z=>U);
Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);
Gate3: component AND2 port map (X=>U,Y=>½,Z=>V);
Gate4: component ¦R2 port map (X=>W,Y=>V,Z=>Y);
5/29 end architecture Struct;
|



  
A First look at VHDL:
Example 3
Digital
‡ Assume that we want to use the
design
previously declared AND3, ¦R3 and INV
Combina- for this structural description of MUX
torial
circuits
configuration Use3InputGates of MUX21 is
Sequential for ½ehav Entities
circuits A
end for; Y
for Struct ½
FSMD for Gate1:INV use entity INV(RTL) C
design
port map (A=>X,Y=>Z);
end for; A Y
VHDL
for All:AND2 use entity AND3(RTL)
port map (A=>X,½=>Y,C=>·1·,Y=>Z);
end for;
for Gate4:¦R2 use entity ¦R3(RTL) Components
port map (A=>X,½=>Y,C=>·0·,Y=>Z);
X
end for; Z
end for;
Y
end configuration Use3InputGates;
X Z
5/30
|



  
A First look at VHDL:
Test bench
Digital
‡ How can we verify the circuit that we
design
made?
Combina- ˜ We have to apply representative stimuli
torial
circuits ˜ to the circuit
˜ and check whether the outputs are correct
Sequential
circuits ‡ A VHDL ¶test bench· can be considered to
FSMD be the top level of a design
design
˜ It instantiates the Design Under Test (DUT)
VHDL ˜ applies stimuli to it
˜ checks whether the stimuli are correct
or
˜ captures the outputs for visualisation in a
waveform viewer

5/31
|



  
A First look at VHDL:
Test bench
Digital
‡ Create a test bench for the behavioral
design
version of the MUX
Combina- entity Testbench is Testbench is A
torial
circuits
end entity Testbench; self-contained: Y
½ MUX21
no ports
Sequential
circuits S

FSMD architecture ½ehavTest of Testbench is

design Signal In1,In2,Select,¦ut : bit;
begin
VHDL DUT: entity MUX21(½ehav) port map (In1, In2, Select, ¦ut);
Stimulus: process is
begin
In1<=¶0·;In2<=¶1·;Select<=¶0·; wait for 20 ns;
Select<=¶1·; wait for 20 ns;
In1<=¶1·;In2<=¶0·; wait for 20 ns;
...
end process Stimulus;
end architecture ½ehavTest;

5/32
|



  
A First look at VHDL:
Re-use
Digital
‡ ¦ften, parts of a design can be re-used in
design
another design
Combina- ‡ New products in industry often contain
torial
circuits 95% of re-used parts and 5% is newly
Sequential
designed: evolutionary design
circuits
‡ VHDL encourages this by the concept of
FSMD ¶Packages·
design
‡ A ¶Package· contains definitions of
VHDL
constant values, component declarations,
user data types, and sub-programs of
VHDL code
‡ ½ut first the concept ¶Library·: a library is
name of directory into which the binary
code resulting from analysis/compilation
5/33 is stored. Default: W¦R
|



  
A First look at VHDL:
Re-use
Digital
Package interface declaration:
design
package Package_name is
Combina- -- constants
torial -- user defined types
circuits -- component declarations
-- sub programs
Sequential end package Package_name;
circuits

FSMD
design

VHDL
How to use a package?

use Library_name.Package_name.all;

U1: entity Package_name.Entity_name(Architecture_name);

5/34
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
˜ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/35
|



  
Signals and Data Types:
Predefined signal types
Digital package Standard is
design type ½it is (¶0·,·1·);
type ½oolean is (False, True);
Combina- type Character is (--ASCII set);
torial type Integer is range implementation_defined;
circuits
type Real is range implementation_defined;
type ½it_vector is (--array of bits);
Sequential
circuits type String is (--array of characters);
type Time is range implementation_defined;
FSMD
end package Standard;
design
½it, ½oolean and Character are enumeration types
VHDL
All standard types are ¶unresolved· (see later for the meaning
of this)

5/36
|



  
Signals and Data Types:
Predefined signal types
Digital
design Examples of integer declarations:
type Year is range 0 to 99;
Combina- type Memory_address is range 65535 downto 0;
torial
circuits
Checked by simulator
Examples of real declarations:
Sequential
circuits type Probability is range 0.0 to 1.0;
type Input_level is range -5.0 to 5.0;
FSMD
design
A ½it_vector is a collection of bits; a value is specified between
VHDL double quotes:
constant State1: bit_vector(4 downto 0) := ´00100µ;
MS½, bit 4 LS½
A String is a collection of characters; a value is specified
between double quotes:
constant Error_message: string
:= ´Unknown error: ask your poor sysop for helpµ;

5/37
|



  
Signals and Data Types:
Predefined signal types
Digital
design Time is a physical type:
type Time is range implementation_defined
Combina-
units
torial fs; Primary unit:
circuits ps = 1000 fs; resolution limit
ns = 1000 ps;
Sequential us = 1000 ns;
circuits
ms = 1000 us; Secondary units
sec = 1000 ms;
FSMD min = 60 sec;
design
hr = 60 min;
end units;
VHDL

Examples of use:
waitfor 20 ns;
constant Sample_period: time := 2 ms;
constant Clock_period: time := 50 ns;

5/38
|



  
Signals and Data Types:
User defined physical types
Digital
design The user may define his/her own physical types:
type Length is range 0 to 1E9
Combina-
units Primary unit:
torial um; resolution limit
circuits mm = 1000 um;
m = 1000 mm;
Metric secondary units
Sequential km = 1000 m;
circuits
mil = 254 um;
inch = 1000 mil;
FSMD foot = 12 inch;
design Imperial secondary units
yard = 3 foot;
end units;
VHDL

5/39
|



  
Signals and Data Types:
User defined enumeration types
Digital
design The user may define his/her own enumeration types:
type FSM_states is (reset, wait, input, calculate, output);
Combina-
torial
circuits
Not all synthesis tools support enumerated types
Sequential
circuits When they do support them, the default encoding is often
straightforward encoding using the minimum number of bits
FSMD
design
¦ften, the default encoding may be over-written by somewhere
specifying something like ´encoding_style is gray_codeµ or by
VHDL
explicitly specifying the encoding for each possible value:
constant reset: bit_vector := ´10000µ;
constant wait: bit_vector := ´01000µ;
constant input: bit_vector := ´00100µ;
constant calculate: bit_vector := ´00010µ;
constant output: bit_vector := ´00001µ;

5/40
|



  
Signals and Data Types:
Array types
Digital
design
The user may define arrays of types:
type 1D_array is array (1 to 10) of integer;
Combina- type 2D_array is array (5 downto 0, 1 to 10) of real;
torial
circuits

eep in mind that a vector of bits has N¦ numerical meaning

Sequential
circuits
and that hence arithmetic operations on vectors of bits make
no sense:
FSMD
design signal ½us,Address : bit_vector (0 to 3);

VHDL ½us <= Address + 1; -- This makes no sense!!!

Solution: via operator overloading (cf. C++):

- two functions ¶+· will exist, one working on integers and
one working on vectors of bits
- the latter is defined in a vendor specific ¶vector
arithmetic package· that should be use·d at the beginning
of your VHDL

5/41
|



  
Signals and Data Types:
Standard logic
Digital
‡ We have seen that we need more logic
design
levels than just ¶0· and ¶1· (e.g. don·t care,
Combina- unknown after setup violation, «)
torial
circuits ‡ Therefore the IEEE defined in standard
Sequential
number 1164 9-valued logic signals and
circuits operations on them: use always those
FSMD instead of ¶bit·!!
design
‡ Exists in unresolved form (std_ulogic) and
VHDL resolved form (std_logic) -- again: see
later for meaning
‡ Exists in single bit and array form:
˜ constant A: std_ulogic := ¶U·; -- unitialized
˜ constant ½: std_logic := ¶U·;
˜ constant C: std_ulogic_vector (0 to 15);
5/42 ˜ constant D: std_logic_vector (15 downto 0);
|



  
Signals and Data Types:
Standard logic
Digital
design library IEEE;
use IEEE.Std_logic_1164.All;
Combina-
torial type std_logic is (
circuits
¶U·, -- uninitialized e.g. after power-up
¶X·, -- strongly driven unknown e.g. after setup violation
Sequential
circuits
¶0·, -- strongly driven logic zero
¶1·, -- strongly driven logic one
¶Z·, -- high impedance e.g. not driven at all
FSMD
design ¶W·, -- weakly driven unknown
¶L·, -- weakly driven logic zero
VHDL ¶H·, -- weakly driven logic one
¶-·); -- don·t care

5/43
|



  
Signals and Data Types:
Assignment to signals
Digital Is the following code valid?
design
signal Z,A,½: std_ulogic;
Combina-
torial Z <= A;
circuits
Z <= ½;
Sequential
circuits No, because:
- all statements are concurrently valid and are not executed
FSMD sequentially as in SW languages
design
- when A=¶0· and ½=¶1·, we have a short circuit
VHDL

A A Resolver
circuit

R
Z Z
½ ½

5/44
|



  
Signals and Data Types:
Assignment to signals
Digital
‡ VHDL is a single assignment language for
design
unresolved data types
Combina- ‡ For resolved data types (std_logic &
torial
circuits std_logic_vector), the resolver circuit is
Sequential
inferred by the synthesis tool
circuits

FSMD
design
A Resolver
signal Z,A,½: std_logic; circuit
VHDL

Z <= A; R
Z <= ½;
½ Z

5/45
|



  
Signals and Data Types:
Assignment to signals
Digital
‡ When an array is assigned to another
design
array, both arrays must have same size
Combina- ‡ Assignment is by position, not by index!!!
torial
circuits
signal Down: std_logic_vector (3 downto 0);
Sequential signal Up: std_logic_vector (0 to 3);
circuits

Up <= Down;
FSMD
design
Which of the two following interpretations is correct?
VHDL

Up(0) Down(3) Up(0) Down(0)

Up(1) Down(2) Up(1) Down(1)

¦R
Up(2) Down(1) Up(2) Down(2)

Up(3) Down(0) Up(3) Down(3)

5/46 Correspondence by position!

|



  
Signals and Data Types:
Assignment to signals
Digital
‡ Assignment to a part of an array is
design
possible
Combina- ‡ Make sure that the direction (to or
torial
circuits downto) is the same as in the declaration
Sequential signal ½us: std_logic_vector (7 downto 0);
circuits
signal A: std_logic_vector (0 to 3);

FSMD Which of the following VHDL codes is correct?

design

½us(0 to 3) <= A; Direction of ½us differs from declaration

VHDL

½us <= A; Array sizes do not match

½us(3 downto 0) <= A; ¦ ! ½us(3) is driven by A(0)

½us(5 downto 4) <= A(0 to 1); ¦ ! ½us(5) is driven by A(0)

½us(5 downto 4) <= A(0 to 1); ¦ ! ½us(4) is driven by A(1)

½us(4 downto 3) <= A(2 to 3); and by A(2): resolved data
5/47 type« use with care!!
|



  
Signals and Data Types:
Assignment to signals
Digital
‡ ¶Concatenation·: bring wire bundles
design
together to assign them to a bigger array
Combina- signal ½yte_bus: std_logic_vector(7 downto 0);
torial
circuits
signal Nibble_busA, Nibble_bus½: std_logic_vector(3 downto 0);

½yte_bus <= Nibble_busA & Nibble_bus½;

Sequential
circuits
Nibble_busA(3)
FSMD Nibble_busA(2)
design ½yte_bus(7) Nibble_busA(1)
½yte_bus(6) Nibble_busA(0)
VHDL ½yte_bus(5)
½yte_bus(4)
½yte_bus(3)
½yte_bus(2)
½yte_bus(1) Nibble_bus½(3)
½yte_bus(0) Nibble_bus½(2)
Nibble_bus½(1)
Nibble_bus½(0)

5/48
|



  
Signals and Data Types:
Assignment to signals
Digital
‡ ¶Aggregation·: alternative method to
design
assign multiple small arrays to a bigger
Combina- array
torial
circuits ‡ Not supported by all synthesis tools!!
Sequential
circuits signal X,Y,Z,T: std_logic_vector(3 downto 0);
signal A,½,C: std_logic;
FSMD
design X <= (A,½,C,C); -- correspondence by position

VHDL Y <= (3 => A, 1 downto 0 => C, 2 => ½);

Z <= (3 => A, 2 => ½, others => C);

T <= (others => ¶0·); -- initialization irrespective of width of T

5/49
|



  
Signals and Data Types:
Generic constants
Digital
‡ Allows to parameterize behavior
design
‡ Enables re-use of entities in slightly
Combina- changing environments
torial
circuits
‡ Makes VHDL much more powerful than
Sequential schematic entry
circuits
‡ Generic constants need to have a value at
FSMD
design
synthesis time!
entity General_mux is
VHDL
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
¦utput : out std_logic);
end entity General_mux;

5/50
|


 Generic constants
  
entity General_mux is
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Digital Select : in integer range 0 to width - 1;
design ¦utput : out std_logic);
end entity General_mux; This is not valid VHDL:
Combina- index is not known at
torial architecture ½ehav of General_mux is
circuits design time! We will
begin replace this by valid
¦utput <= Input(Select); code later!
Sequential
circuits
end architecture ½ehav;

entity Testbench is
FSMD
design
end entity Testbench;

architecture ½uild1 of Testbench is

VHDL
constant Input_size : integer := 8;
signal A : std_logic_vector (Input_size-1 downto 0);
signal S : integer range 0 to Input_size - 1;
signal ½ : std_logic;
begin
DUT: entity General_mux(½ehav)
generic map (width => Input_size)
port map (Input => A, Select => S, ¦utput => ½);
...
5/51 end architecture ½uild1;
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
˜ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/52
|



  
Logical ¦perators

Digital
‡ List of logical operators: not, and, or, xor,
design
nand, nor
Combina- ‡ Precedence:
torial
circuits ˜ ¶not· has highest precedence
Sequential
˜ all others have equal precedence, lower than
circuits ¶not·
FSMD ‡ Logical operators are predefined for
design
following data types: bit, bit_vector,
VHDL boolean, std_logic, std_logic_vector,
std_ulogic, std_ulogic_vector
‡ A logical operator may work on an array:
˜ arrays should have same size
˜ elements are matched by position

5/53
|



  
Logical ¦perators

Digital
design

library IEEE;
Combina- use IEEE.Std_Logic_1164.All;
torial
circuits
entity Gate is
Sequential
port( A,½,C: in std_logic;
circuits Z: out std_logic);
end entity Gate;
FSMD
design architecture Logical of Gate is
begin
VHDL Z <= A and not(½ or C);
end architecture Logical;

5/54
|



  
Logical ¦perators

Digital
design
library IEEE;
Combina- use IEEE.Std_Logic_1164.All;
torial
circuits entity Gate is
generic(width : integer range 0 to 31);
Sequential port( A,½,C: in std_logic_vector(width-1 downto 0);
circuits
Z: out std_logic_vector(width-1 downto 0));
end entity Gate;
FSMD
design
architecture Logical of Gate is
begin
VHDL
Z <= A and not(½ or C);
end architecture Logical;

5/55
|



  
Relational ¦perators

Digital
‡ List of relational operators: <, <=, =>, >, =,
design
/=
Combina- ‡ Relational operators return a boolean
torial
circuits
‡ ½oth operands need to be of the same
Sequential type
circuits
‡ A relational operator may work on an
FSMD
design
array:
˜ arrays may have different size!!
VHDL
˜ They are left alligned and the number of bits
equal to the smallest array are compared; the
comparison is done bit by bit, from left to right
˜ Remember: vectors of bits do not have a
numerical meaning!! However, this comparison
works on vectors of bits with the meaning of an
unsigned integer when both vectors have equal
5/56 length
|



  
Relational ¦perators
library IEEE
use IEEE.Std_Logic_1164.All;
Digital
What is the
design entity Compare is value of Z?
port( A: in std_logic_vector(3 downto 0);
½: in std_logic_vector(0 to 4); TRUE?
Combina-
torial Z: out boolean); FALSE?
circuits end entity Compare;

Sequential architecture Relational of Compare is

circuits
1110
begin is compared to
Z <= TRUE when A<½ else FALSE; 1011
FSMD
design
end architecture Relational; by bit position
from left to
entity Testbench right;
VHDL
end entity Testbench; in the 2nd
position
architecture ½uild1 of Testbench is A(2) > ½(1)
signal A: std_logic_vector(3 downto 0) := ´1110µ; hence (A<½)
signal ½: std_logic_vector(0 to 4) := ´10111µ; is FALSE
signal Z: boolean;
begin
DUT: entity Compare(Relational)
port map (A => A, ½ => ½, Z => Z);
5/57 end architecture ½uild1;
|



  
Arithmetic ¦perators

Digital
‡ List of arithmetic operators: +, -, *, /, **
design
(exponential), abs (absolute value), mod
Combina- (modulus), rem (remainder)
torial
circuits ‡ They are defined on types integer and real
Sequential
(except mod and rem) and not on vectors
circuits of bits; use overloading package for the
FSMD latter (vendor dependent)
design
‡ ½oth operands have to be of same type;
VHDL different ranges are allowed
‡ A variable of physical type (e.g. time) may
be multiplied by an integer or real and will
still return a variable of the physical type

5/58
|



  
Arithmetic ¦perators

Digital entity Add is

design port ( A,½: in integer range 0 to 7;
Z: out integer range 0 to 14);
Combina- end entity Add;
torial
circuits
architecture ½ehav of Add is
begin
Sequential
circuits Z <= A + ½;
end architecture ½ehav;
FSMD
design

VHDL

5/59
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
˜ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/60
|



  
Concurrent Statements

Digital
‡ All statements are concurrent and are
design
continuously valid: this mimics the
Combina- behavior of hardware, where all gates
torial
circuits operate concurrently
Sequential
circuits entity Concurrent is
port ( A,½,C,D: in std_logic; Schematic:
FSMD Y,Z: out std_logic);
design
end entity Concurrent;
A
VHDL
architecture Struct of Concurrent is Y
½
begin
NAND1: entity NAND2 port map (A,½,Y); C
Z
NAND2: entity NAND2 port map (C,D,Z); D
end architecture Struct;

What is the difference in behavior when NAND1 is specified

after NAND2?
5/61
|



  
Concurrent Statements

Digital
‡ All statements are concurrent and are
design
continuously valid: this mimics the
Combina- behavior of hardware, where all gates
torial
circuits operate concurrently
Sequential
circuits entity Concurrent is
port ( A,½,C,D: in std_logic; Schematic:
FSMD Y,Z: out std_logic);
design
end entity Concurrent;
A
VHDL
architecture Struct of Concurrent is Y
½
begin
NAND2: entity NAND2 port map (C,D,Z); C
Z
NAND1: entity NAND2 port map (A,½,Y); D
end architecture Struct;

½ehavior is exactly the same!!!

5/62
|



  
Concurrent Statements
Does this schematic specify sequential ½ehavior?
Digital
design
Yes Schematic:

Combina- No
torial
circuits
A
entity Concurrent is ½ T1
Sequential
port ( A,½, D: in std_logic;
circuits Z: out std_logic); Z
end entity Concurrent; D
FSMD
design architecture Struct of Concurrent is
signal T1: std_logic;
VHDL begin
NAND2: entity NAND2 port map (T1,D,Z);
NAND1: entity NAND2 port map (A,½,T1);
end architecture Struct;

½oth gates continuously update their outputs

5/63
|



  
Simulation

Digital
‡ This continuously updating of outputs
design
poses problems to the simulator: even if
Combina- nothing in the circuit changes, the
torial
circuits simulator has to compute continuously
the ¶new· outputs of all gates
Sequential
circuits ‡ Solution: event-driven simulation
FSMD ˜ a statement is only re-evaluated when one or
design more of its input signals changes (i.e. when an
event occurs at one of its inputs)
VHDL
˜ we say that a statement is sensitive to all its
input signals, because an event at any input
signals triggers a re-evaluation
˜ keep in mind that this mechanism is only for
making simulation fast while maintaining the
same behavior as in reality, where all gates
work continuously!!
5/64
|



  
Simulation

Digital
‡ How is an event-driven simulator
design
practically implemented?
Combina- 1. Put all statements with at least one changed input in the
torial
circuits
¶process execution queue·
2. Execute all statements in the process execution queue
Sequential one by one (or concurrently if the simulator is executed
circuits
on a parallel computer) without updating the output signals

FSMD 3. After all statements in the process execution queue are

design processed, update the output signals
4. Add all statements to the process execution queue that
VHDL
have an event because of the updated output signals
5. Repeat until the process execution queue is empty
6. Advance system time to the next time where a timed
event is planned (e.g. testbench: waitfor 20 ns)

Delta cycle
Delta cycle convergence

5/65
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND1 NAND1
NAND2
Q

Q·
Step 1: Put statements with input
T1 T2 event in PEQ
5/66
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1 NAND1
NAND2
Q

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/67
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1
NAND2 NAND1
NAND2
Q

Q·
Step 3: Update outputs
T1 T2
5/68
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND2 NAND1
NAND2
Q

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/69 End Delta cycle 1 of T1
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q <= 0
½ NAND2 NAND1
NAND2
Q

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/70
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q <= 0
½ NAND2 NAND1
NAND2
Q

Q·
Step 3: Update outputs
T1 T2
5/71
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND1 NAND1
NAND2
Q

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/72 End Delta cycle 2 of T1
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1 NAND1
NAND2
Q

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/73
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1 NAND1
NAND2
Q

Q·
Step 3: Update outputs
T1 T2
5/74 ¦utput does not change
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND1
NAND2
Q

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/75 End Delta cycle 3 of T1: convergence
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND1
NAND2
Q

Q·
Step 6: Advance system time
T1 T2
5/76
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1
NAND2
Q <= 1
NAND2
Q

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/77 NAND2 computed using this Q·, not the remembered
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 1
½ NAND1
NAND2
Q <= 1
NAND2
Q

Q·
Step 3: Update outputs
T1 T2
5/78
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND1

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/79 End Delta cycle 1 of T2
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 0
½ NAND1

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/80
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q· <= 0
½ NAND1

Q·
Step 3: Update outputs
T1 T2
5/81
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

½ NAND2

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/82 End Delta cycle 2 of T2
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q <= 1
½ NAND2

Q·
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/83
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL ¦utputs Queue Queue
A T1 T2
Q <= 1
½ NAND2

Q·
Step 3: Update outputs
T1 T2
5/84 ¦utput does not change
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

Q·
Step 4: Add statements with event
T1 T2 to PEQ
5/85 End Delta cycle 3 of T2: convergence
|



  
Simulation
entity Flipflop is A
Q·
Digital port ( A,½: in std_logic;
design Q,Q·: out std_logic);
end entity Flipflop; Q
Combina- ½
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q·,½,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q·);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2

Q·
Step 6: Advance system time
T1 T2
5/86
|



  
Process

Digital
‡ Sometimes, the combinatorial equation in
design
a single statement becomes very
Combina- complicated:
torial A
circuits ½
C
Sequential
circuits D Y

entity Complex is E
FSMD
port( A,½,C,D,E,F,G,H,I,J: F S
design
in std_logic; G
Y,Z: out std_logic);
VHDL H
end entity Complex;
I Z
architecture Struct of Complex is J
begin
Y <= ((A nand ½) nand (C nand D))
when (S = ¶1·) else
((E nand F) nand (G nand H));
Z <= I nand J;
end architecture Struct;
5/87
|



Unfortunately, in VHDL
  
Process terminology they are
also called ¶Statements·

Digital
‡ Therefore a process has been defined:
design
˜ a process acts as a single statement that is
Combina-
executed concurrently with all other
torial statements
circuits
˜ inside a process, commands are executed
Sequential sequentially in the order they are listed. This
circuits makes it easy to break down a very
complicated statement into a list of smaller
FSMD
design
commands
˜ to pass data from one command to the other,
VHDL we may declare temporary variables; they do
not have necessarily a physical realization
˜ a statement, and hence also a process, is
sensitive to all its input signals; to facilitate
finding out what the input signals of a process
are, since they can occur in any command, we
have to explicitly add them to a sensitivity list.
A process is recalculated when a signal in the
5/88 sensitivity list has an event.
|



  
Process

Digital
Syntax of process:
design
Process_name: process (sensitivity_list) is
Combina- -- variable declarations;
torial begin
circuits -- sequential commands
end process Process_name;
Sequential
circuits

FSMD
Syntax of variable declaration:
design
variable Variable_name: type;
VHDL

Syntax of variable assignment:

Variable_name := expression;

When assigning to variable Ä :=

When assigning to signal Ä <=
5/89
|



   Process
‡ Rewrite the example using a process:
Digital
design entity Complex is T1 and T2 have no
port( A,½,C,D,E,F,G,H,I,J: physical meaning since
Combina- in std_logic; each refers to 2 different
torial Y,Z: out std_logic); physical wires
circuits end entity Complex;
T1 T2
Sequential architecture Struct of Complex is
circuits Sensitivity list
begin
Y_process: process (A,½,C,D,E,F,G,H,S) is
FSMD
design
variable T1,T2: std_logic;
begin A
if (S=¶1·) then ½
VHDL
T1 := A nand ½; C
T2 := C nand D; Y
D
else
T1 := E nand F; E
T2 := G nand H; F S
end if; G
Y <= T1 nand T2;
H
end process Y_process;
Z <= I nand J; I Z
5/90 end architecture Struct; J
|



  
Process

Digital
‡ Processes and delta cycle convergence.
design
What is the behavior of following process:
Combina- Example: process (A,½,M) is
torial
circuits
begin
Y <= A; ¦ld M!!! M gets
M <= ½; only new value
Sequential at end of process
circuits Z <= M;
end process Example;
FSMD
design 1. Assume event at ½ with new value ½·
2. Process Example is executed once sequentially. Following
VHDL outputs are remembered: Y· <= A; M· <= ½·; Z· <= M;
3. Process Example suspends (i.e. is executed once completely).
Y, M and Z get their new values Y·, M·, Z·.
4. Since M is in the sensitivity list, the Example process is
placed again in the Process Execution Queue.
5. Process Example is executed: Yµ <= A; Mµ <= ½·; Zµ <= M·;
6. ¦utputs Y, M and Z get their new values Yµ, Mµ, Zµ.
7. No signals of the sensitivity list changed => delta cycle
5/91 convergence
|



  
Process

Digital
‡ Processes and delta cycle convergence.
design
What is the behavior of following process:
Combina-
torial Example: process (A,½,C,D) is
circuits begin
Z <= A + ½;
Sequential Z <= C + D;
circuits
end process Example;

FSMD
design 1. Assume event at ½ with new value ½·
2. The commands of Process Example are executed
VHDL sequentially. First following output is remembered:
Z· <= A + ½·;
3. Next, the second command is executed and following output
is remembered: Z· <= C + D. This overwrites the previously
remembered Z·
4. Process Example suspends and hence signal Z is updated
with its new value C + D
When the same two statements would have occurred outside a
process, both would drive signal Z and a resolver would be
necessary
5/92
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ˜ Sequential construction statements
VHDL ‡ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/93
|



  
Sequential construction
statements
Digital
‡ Sequential construction statements are
design
only allowed within a process!!!
Combina- ‡ There are 3 sequential construction
torial
circuits statements: IF, CASE, F¦R
Sequential IF statement:
circuits

if condition then
FSMD -- sequential statements
design
else
-- sequential statements
VHDL
end if;
The first condition which
turns out to be TRUE
determines which
sequential statements are
executed: built-in priority
5/94
multiple IF statements:
if condition1 then
-- sequential statements
elseif condition2 then
-- sequential statements
elseif condition3 then
-- sequential statements
else
-- sequential statements
end if;
|




 
Sequential construction
statements
case Expression is
Digital when Value_1 =>
design
-- sequential statements
when Value_2 =>
Combina-
torial
-- sequential statements
circuits -- etc.
end case; Requirements:
Sequential
circuits
1. All possible values should
be specified
FSMD Example: process (A,½,C,X) is
design begin 2. The values should be
case X is constant and known at
VHDL when 0 to 4 => design time
Z <= ½; 3. The values should have the
when 5 => same type as the
Z <= C; expression
when 7 | 9 =>
Z <= A;
when others =>
Z <= ¶0·;
end process Example;
5/95
|




 
Sequential construction
statements
Digital
design for I in 0 to 3 loop
-- sequential statements
Combina-
end loop;
torial
circuits Remarks:

Sequential 1. The loop variable must not be declared

circuits
2. The synthesis tool will unfold the loop and create logic for
each iteration of the loop. Then, it will start minimizing the
FSMD
design
complete circuit

VHDL

5/96
|



  
Sequential construction
statements
entity General_mux is
Digital generic (width : integer);
design
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
Combina-
torial
¦utput : out std_logic);
circuits end entity General_mux;

Sequential architecture ½ehav of General_mux is

circuits begin We indicated that
¦utput <= Input(Select); this is not valid VHDL:
FSMD end architecture ½ehav; index is not known at
design
design time! We will
replace this now by
VHDL
valid code using the
loop construct.

5/97
|



  
Sequential construction
statements
Digital
design entity General_mux is
generic (width : integer);
Combina-
port ( Input : in std_logic_vector (width - 1 downto 0);
torial Select : in integer range 0 to width - 1;
circuits ¦utput : out std_logic);
end entity General_mux;
Sequential
circuits
architecture ½ehav of General_mux is
begin
FSMD Selector: process (Input, Select) is
design
begin
for I in 0 to width-1 loop
VHDL
if Select=I then
¦utput <= Input(I);
end if;
end loop;
end process Selector;
end architecture ½ehav;

5/98
|



  
Variables

Digital
‡ A variable can only be used within a
design
process
Combina- ‡ A variable is updated immediately; a
torial
circuits signal is stored in the signal update
Sequential
queue till the process suspends
circuits
‡ Variables may be assigned to signals and
FSMD vice versa
design
‡ Variables are used as intermediate values
VHDL
to facilitate the specification of the
process; when the value of a variable
needs to be accessible outside the
process, it should be assigned to a signal

5/99
|



  
Variables
With which hardware schematic does following code correspond?
Digital
design entity Parity is
generic (width : integer);
Combina- port (A: in std_logic_vector (0 to width-1);
torial
circuits
¦dd: out std_logic);
end entity Parity; This is the HW structure
as it is given to the synthesis
Sequential
circuits architecture Struct of Parity is tool. The synthesis tool
begin will optimize away the xor
FSMD Parity: process(A) is with constant ¶0· input
design variable Temp: std_logic; and will transform it to
begin a binary tree of less depth
VHDL Temp := ¶0·;
for I in A·low to A·high loop
Temp := Temp xor A(I); 0 Temp
end loop; A(0)
¦dd <= Temp;
end process Parity; Temp
end architecture Struct; A(1)
¦dd
A(2)
5/100
|



  
Rising clock edge
With which function does following code correspond?
Digital
design
entity What is
port (D,Clk: in std_logic;
Q: out std_logic);
Combina-
torial end entity What;
circuits Since there is no ELSE part
architecture RTL of What is the previous Q value has
Sequential begin to be remembered for the case
circuits process (D, Clk) is where Clk=¶0·.
begin The synthesis tool will hence
FSMD if (Clk=¶1·) then infer a latch instead of just
design
Q <= D; combinatorial logic!!!
end if;
VHDL end process; ½eware of unintended latches
end architecture RTL; when ELSE parts are omitted

With a latch, not with a D-flip-flop!!

When a Clk-event occurs and Clk is low, nothing happens

When a Clk-event occurs and Clk is high, the D input is copied
to the Q output
When a D-event occurs and Clk is high, the D input is copied to
5/101 the Q output => hence a latch: when Clk is high, Q follows D
|



  
Rising clock edge
How do we describe a rising clock edge?
Digital
design
Method 1: WAIT UNTIL
Combina-
entity DFlipFlop is
torial
circuits port (D,Clk: in std_logic;
Q: out std_logic);
Sequential end entity DFlipFlop;
circuits
architecture RTL of DFlipFlop is
FSMD begin
design process is This is not synthesisable
begin
VHDL wait until Clk·event and Clk=¶1·;
Q <= D;
end process;
end architecture RTL;

5/102
|



  
Rising clock edge
How do we describe a rising clock edge?
Digital
design Method 2: Sensitivity list Preferred method!

Combina- entity DFlipFlop is

torial port (D,Clk: in std_logic;
circuits
Q: out std_logic);
end entity DFlipFlop;
Sequential
circuits
architecture RTL of DFlipFlop is
begin
FSMD
design
process (D,Clk) is
begin
if (Clk·event and Clk=¶1·) then
VHDL
Q <= D;
end if;
end process;
end architecture RTL;

5/103
|



  
Rising clock edge
How do we describe combinatorial circuits with registered outputs?
Digital
design
A
Combina- ½ Z
torial
circuits
C
Sequential Method 1: WAIT UNTIL
circuits
D
entity RegisteredCircuit is
FSMD port (A,½,C,D,Clk: in std_logic;
design Z: out std_logic);
end entity RegisteredCircuit; ¶Wait until· has to be
VHDL first line of process,
architecture RTL of RegisteredCircuit is followed by
begin the description of the
process is combinatorial circuit
begin
wait until Clk·event and Clk=¶1·;
-- combinatorial circuit
Z <= (A and ½) or (C and D);
end process;
end architecture RTL;
5/104
|



  
Rising clock edge
How do we describe combinatorial circuits with registered outputs?
Digital
design
A
Combina- ½ Z
torial
circuits
Method 2: Sensitivity list
C
Sequential
circuits entity RegisteredCircuit is D
port (A,½,C,D,Clk: in std_logic;
FSMD
Z: out std_logic);
design end entity RegisteredCircuit;
¶if Clk·event· has to be
first line of process,
VHDL architecture RTL of RegisteredCircuit is
with the description
begin
of the combinatorial
process (A,½,C,D,Clk) is
circuit in the THEN
begin
part and with no
if (Clk·event and Clk=¶1·) then
ELSE part
-- combinatorial circuit
Z <= (A and ½) or (C and D);
end if;
end process;
end architecture RTL;
5/105
|



  
Rising clock edge

Digital
‡ The amount of logic we describe in the
design
combinatorial part, determines the
Combina- combinatorial delay
torial
circuits ‡ It hence determines the maximum clock
Sequential
frequency with which we can clock the
circuits flip-flop
FSMD ‡ Re-timing requires re-writing the VHDL
design
code
VHDL

5/106
|



  
Rising clock edge
How do we describe flip-flops with asynchronous reset?
Digital
design

entity DFlipFlop is
Combina-
port (D,Clk, Reset: in std_logic;
torial
circuits Q: out std_logic);
end entity DFlipFlop;
Sequential
circuits architecture RTL of DFlipFlop is
begin
FSMD process (D, Clk, Reset) is
design begin
if (Reset = ¶1·) then
VHDL Q <= ¶0·;
elseif (Clk·event and Clk=¶1·) then
Q <= D;
end if;
end process;
end architecture RTL;

5/107
|



  
Rising clock edge
How do we describe flip-flops with synchronous reset?
Digital
design
entity DFlipFlop is
port (D,Clk, Reset: in std_logic;
Combina-
Q: out std_logic);
torial
circuits end entity DFlipFlop;

Sequential architecture RTL of DFlipFlop is

circuits begin
process (D, Clk, Reset) is
FSMD begin
design if (Clk·event and Clk=¶1·) then
if (Reset=¶1·) then
VHDL Q <= 0;
else
Q <= D;
end if;
end if;
end process;
end architecture RTL;

5/108
|



  
Finite State Machine

Digital Start=0
design

Wait
Combina- Reset Start=1 00
torial ¦ut ¦utput Start=1
circuits Up=1 Up=0
put
logic
Sequential
circuits
Up1 Down3
State 01 11
Reg CurrentState
FSMD
design

Next NextState Up2 Down2

VHDL
state 10 10
logic

Up3 Down1
11 01
Start Up

5/109
|



  
Finite State Machine
entity FSM is
Digital
port ( Start, Up, Reset, Clk: in std_logic; Start=0
design ¦utput: out std_logic_vector(0 to 1));
end entity FSM;
Wait
Combina- 00
torial architecture ½ehav of FSM is Start=1 Start=1
circuits type FSM_States = (Wait,Up1,Up2, Up=1 Up=0
Up3,Down1,Down2,Down3);
Sequential signal CurrentState, NextState :
circuits
Up1 Down3
FSM_States; 01 11
begin
FSMD
design
¦utputLogic:
process(CurrentState) is
« Up2 Down2
VHDL
end process ¦utputLogic; 10 10
NextStateLogic:
process(CurrentState,Start,Up) is
«
end process NextStateLogic; Up3 Down1
StateRegister: 11 01
process(NextState,Clk,Reset) is
«
end process StateRegister;
5/110 end architecture ½ehav;
|



  
Finite State Machine

Digital Start=0
design

Wait
Combina- 00
torial ¦utputLogic: Start=1 Start=1
circuits process(CurrentState) is Up=1 Up=0
begin
Sequential case CurrentState is
circuits
Up1 Down3
when Wait => 01 11
¦utput <= ´00µ;
FSMD
design
when Up1|Down1 =>
¦utput <= ´01µ;
when Up2|Down2 => Up2 Down2
VHDL
¦utput <= ´10µ; 10 10
when Up3|Down3 =>
¦utput <= ´11µ;
end case;
end process ¦utputLogic; Up3 Down1
11 01

5/111
|



  
Finite State Machine
NextStateLogic:
Digital
process(CurrentState,Start,Up) is Start=0
design begin
case CurrentState is
Wait
Combina- when Wait =>
Start=1 00 Start=1
torial if (Start=¶0·) then
circuits NextState <= Wait; Up=1 Up=0
elseif (Up=¶1·) then
Sequential NextState <= Up1;
circuits
Up1 Down3
else 01 11
NextState <= Down3;
FSMD
design
end if;
when Up1 =>
NextState <= Up2; Up2 Down2
VHDL
when Up2 => 10 10
NextState <= Up3;
when Up3|Down1 =>
NextState <= Wait;
when Down3 => Up3 Down1
NextState <= Down2; 11 01
when Down2 =>
NextState <= Down1;
end case;
5/112 end process NextStateLogic;
|



  
Finite State Machine

Digital Start=0
design

Wait
Combina- 00
torial Start=1 Start=1
circuits Up=1 Up=0

Sequential
StateRegister:
circuits process(NextState,Clk,Reset) is Up1 Down3
begin 01 11
FSMD if Reset=¶1· then
design CurrentState <= Wait;
elseif (Clk·event and Clk=¶1·) then
VHDL CurrentState <= NextState; Up2 Down2
end if; 10 10
end process StateRegister;

Up3 Down1
11 01

5/113
|



  
Language based HW design:
a VHDL primer
Digital
‡ Introduction
design
‡ A first look at VHDL
Combina-
torial
‡ Signals and data types
circuits
‡ VHDL operators
Sequential
circuits
‡ Concurrent versus sequential
statements
FSMD
design ‡ Sequential construction statements
VHDL ˜ Higher performance, less portability:
e.g. synthesis issues for Xilinx

5/114
|



  
Resource sharing
What is the circuit corresponding to: A ½ A C
Digital
design
if Sel = ¶1· then
Z <= A + ½;
Combina-
else + +
torial
circuits Z <= A + C;
end if;
Sequential Sel
circuits MUX
This is kind of stupid, since both
FSMD additions are mutually exclusive: Z
design it is hence not necessary to
implement 2 adders.
VHDL ½ C A
Some synthesis tools are capable
to recognize this (often only within MUX
Sel
the scope of a process) and
transform this into the shared use
of one adder for both additions.
Xilinx Foundation Series performs
+
this optimization within a
hierarchical level.
5/115 Z
|



  
Resource sharing
If the synthesis tool does not do ½ C A
Digital
design this optimization automatically,
you should re-write your code: MUX
Sel
Combina-
torial
circuits
if Sel = ¶1· then
X := ½;
else
Sequential +
circuits X := C;
end if;
Z <= A + X; Z
FSMD
design

VHDL
The VHDL coding style together with the capabilities of the
synthesis tool determine the circuit that is eventually
synthesized.

5/116
|



  
Using Logi½L¦X in VHDL

Digital
‡ Logi½L¦X modules lead to highly efficient
design
FPGA implementations
Combina- ‡ The Logi½L¦X module generator creates,
torial
circuits apart from the FPGA implementation, also
Sequential
a behavioral level VHDL module for
circuits simulation!
FSMD ‡ How to use Logi½L¦X modules in your
design
VHDL code:
VHDL ˜ use the package containing the Logi½L¦X
modules: library My_Library; use
My_Library.My_Package.all;
˜ instantiate the entity
‡ Using Logi½L¦X makes your VHDL
implementation more efficient on Xilinx
FPGA but less portable to other devices!!
5/117
|



  
Encoding of State Machines

Digital
‡ The default encoding in Foundation
design
Express is one-hot since this matches
Combina- well with the structure of a CL½ (little bit
torial
circuits of combinatorial logic in front of a D-flip-
flop)
Sequential
circuits ‡ The encoding can be specified in the
FSMD VHDL code:
design
type State_Type is (S1, S2, S3, S4);
VHDL attribute ENUM_ENC¦DING: string;
attribute ENUM_ENC¦DING of State_Type: type is ´11 10 01 00µ;

5/118
|



  
Safe state machines

Digital
‡ Assume a state
design
machine of three
Combina- states, encoded with
torial NextStateLogic:
circuits 2 bits process(CurrentState) is
‡ What would happen begin
Sequential case CurrentState is
circuits when the state when Idle =>
machine enters the NextState <= S1;
FSMD
when S1 =>
design
4th state, due to NextState <= S2;
some error (noise, when S2 =>
VHDL
NextState <= Idle;
power-up, «)? Will it when others =>
be able to recover? NextState <= Idle;
end case;
‡ Make provisions for end process NextStateLogic;
this situation in your
VHDL code:
5/119
|



  
Family specific issues

Digital
‡ Not all families provide per flip-flop both
design
asynchronous set as well as reset.
Combina- ‡ Check what your family provides before
torial
circuits you write VHDL
Sequential
circuits process (Clk, Rst, Set) is Can only be implemented
begin efficiently when the
FSMD if Rst = ¶1· then family has both an
design
Q <= ¶0·; asynchronous set
elseif Set = ¶1· then as well as reset
VHDL
Q <= ¶1·;
elseif Clk·event and Clk = ¶1· then
-- actions
end if;
end process;

5/120
|



  
Family specific issues

Digital
‡ Always use Logi½L¦X for RAM, because
design
RAM would otherwise be created out of
Combina- separate flip-flops
torial
circuits

Sequential
circuits

FSMD
design

VHDL

5/121
|



  
I/¦ buffer types

Digital
‡ Put all the core logic in one entity
design
‡ In a higher hierarchical level, instantiate
Combina- the I/¦ buffers as well as the core logic
torial
circuits
‡ The hierarchy hence becomes
Sequential ˜ Top level: test bench instantiating DUT
circuits
˜ DUT: Instantiation of core logic and I/¦ buffers
FSMD ˜ Core logic: real design
design

VHDL

5/122
|



  
I/¦ buffer types
How to force a 3-state output buffer:
Digital Enable
design if (Enable = ¶1·) then
¦ut_pad
¦ut_pad <= ½us_out; ½us_out
Combina- else
torial
circuits
¦ut_pad <= ¶Z·;
end if;
Sequential
circuits

FSMD
design
How to force a bidirectional buffer:
VHDL
½us_in <= ½idi_pad;
process (Enable, ½us_out) is
Enable
begin
if (Enable = ¶1·) then ½us_out
½idi_pad <= ½us_out; ½idi_pad
else
½idi_pad <= ¶Z·;
end if; ½us_in
end process;
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I/¦ buffer types
How to force a bidirectional buffer with registered output:
Digital
design
½us_in <= ½idi_pad;
process (Enable,Q) is
begin
Combina-
torial if (Enable = ¶1·) then
circuits ½idi_pad <= Q;
else
Sequential ½idi_pad <= ¶Z·;
circuits end if;
end process;
FSMD process (Clk, ½us_out) is
design
begin
if Clk·event and Clk = ¶1· then
VHDL Q <= D;
end if;
end process; Clk Enable

½us_out
D Q ½idi_pad

½us_in

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I/¦ buffer types
How to force a pull-up resistor at an input:
Vcc
Digital entity Pullup_in is
design port ( In_pad: in std_logic; In_pad
Core_in: out std_logic); Core_in
Combina- end entity Pullup_in;
torial
circuits
architecture RTL of Pullup_in is
Sequential
circuits component PULLUP
port (¦: out std_logic);
FSMD end component PULLUP;
design
component I½UF
VHDL port (I: in std_logic; ¦: out std_logic);
end component I½UF;

signal Dummy: std_logic;

begin
Dummy <= In_pad;
PU: component PULLUP port map (Dummy);
½uf: component I½UF port map (Dummy,Core_in);
end architecture RTL;
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Using the Global Set Reset block

Digital
design entity ¦neHot is
port ( Rst, Clk: in std_logic;
Combina- Q: out std_logic_vector (0 to 3));
torial end entity ¦neHot;
circuits
architecture ½ehav of ¦neHot is
Sequential
circuits
component STARTUP
port (GSR: out std_logic);
FSMD end component STARTUP;
design

begin
VHDL
U1: component STARTUP port map (Rst => GSR);
if Rst = ¶1· then
Q <= ´0001µ;
elseif Clk·event and Clk = ¶1· then
Q <= Q(1 to 3) & Q(0);
endif;
end architecture RTL;

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Clock Networks

Digital
‡ Foundation Express synthesizes
design
automatically clock buffers
Combina- ‡ Check whether you do not need more
torial
circuits clock buffers than are available in the
Sequential
target family
circuits

FSMD
design

VHDL

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