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Contents:
Introduction
Block Diagram and Pin Description of the 8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timer
Interrupt
Microprocessors:
General-purpose microprocessor
CPU
GeneralPurpose
Microprocessor
Data Bus
RAM
ROM
I/O
Port
Address Bus
General-Purpose Microprocessor System
Timer
Serial
COM
Port
Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU
I/O
Port
RAM ROM
Serial
Timer COM
Port
A single chip
Microcontroller
Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
for applications in which cost,
power and space are critical
single-purpose
Salient Features
(1). 8 bit microcontroller originally developed by Intel in 1980.
(2). High-performance CMOS Technology.
(3). Contains Total 40 pins.
(4). Address bus is of 16 bit & data bus is of 8 bit.
(5). 4K bytes internal ROM (program).
(6). 128 bytes internal RAM (data).
(7). Four 8-bit I/O ports.
(8). Two 16-bit timers.
(9). Serial interface Communication.
(10). 64K external code & data memory space.
(11). 210 bit-addressable locations.
(12). Internal memory consists of on-chip ROM and on-chip data RAM.
(13). 8051 implements a separate memory space for programs (code) and data.
(14). Operating frequency is 24MHz-33MHz.
(15). +5V Regulated DC power supply is required to operate .
(16). It has four 8 bit ports, total 32 I/O lines.
(17). RAM, ROM, I/O ports, one serial port and timers are all on-chip.
(18). 6-interrupts (2 are external with 2 priority levels).
(19). Low-power Idle and Power-down Modes.
(20). Full duplex UART.
(21). 8051 has 21 special function registers (SFRs).
8031
8051
ROM
NO
4kB UVEPROM
8052
4kB
8kB
RAM (Bytes)
128
128
128
256
TIMERS
2
I/O PINS
32
32
32
32
ROM
RAM
I/O
Pins
Timer
Interrr
upt
Vcc
Packag
ing
AT89C5
1
4K
128
32
5V
40
AT89LV
51
4K
128
32
3V
40
AT89C1
051
1K
64
15
3V
20
AT89C2
051
2K
128
15
3V
20
AT89C5
2
8K
128
32
5V
40
AT89LV
52
8K
128
32
3V
40
11
12
Registers
A
B
R0
DPTR
DPH
DPL
R1
R2
PC
PC
R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051
ACC
B
PSW
SP
DPTR
IP
PMODE
PCON
TMODE
TCON etc.
14
Register
PC
ACC
B
PSW
SP
DPTR
RAM are all zero.
Reset Value
0000
0000
0000
0000
0007
0000
Special Function
Registers
16
B Register
(1). B register or accumulator B is used along
with the accumulator for multiply and divide
operations.
(2). MUL AB: multiplies 8 bit unsigned values in A
and B. and leaves the 16 bit result in A (low
byte) and B (high byte).
(3). DIV AB: divided A by B, leaving the integer
result in A and remainder in B.
(4). B register is bit-addressable.
17
- ACC : Accumulator.
- B : B register.
- PSW : Program Status Word.
- SP: Stack Pointer.
- DPTR : Data Pointer (DPH, DPL).
Interrupt control:
-IE : Interrupt Enable.
-IP : Interrupt Priority.
I/O Ports:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
- TL0
- TH1
- TL1
Serial I/O:
- SCON : Serial port control.
- SBUF : Serial data registers.
Other:
- PCON : Power control
21
Stack Pointer
(1). Stack pointer (SP) is an 8-bit register at
address 81H.
(2). It contains the address of the data item
currently on top of the stack.
(3). Stack operations include pushing data on the
stack and popping data off the stack.
(4). Pushing increments SP before writing the
data
(5). Popping from the stack reads the data and
decrements the SP
(6). 8051 stack is kept in the internal RAM
(7). Depending on the initial value of the SP,
stack can have different sizes
22
(8). Example: MOV SP,#5FH
23
8k
32k
0000H
0000H
0FFFH
DS5000-32
8751
AT89C51
1FFFH
8752
AT89C52
7FFFH
30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0
7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
Register Bank 3
Register Bank 2
Register Bank 1) Stack(
Register Bank 0
27
List of Registers
(*Denotes the SFRs)
30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0
8051
Schematic
Pin out
8051
Foot Print
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8051
(8031)
(8751)
(8951)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
P0.0(AD0
)P0.1(AD1)
P0.2(AD2
)P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
)P2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
The 8051
Assembly Language
Overview
Data transfer instructions
Addressing modes
Data processing (arithmetic and
logic)
Program flow instructions
dest source
Exchange instructions
XCH a, byte
;exchange accumulator and byte
XCHD a, byte ;exchange low nibbles of
;accumulator and byte
Addressing Modes
Immediate Mode specify data by its value
mov A, #0
mov B, #11
mov DPTR,#7521h
;DPTR = 0111010100100001
Addressing Modes
Immediate Mode continue
MOV DPTR,#7521h
MOV DPL,#21H
MOV DPH, #75
COUNT EGU 30
~
~
0RG 200H
MYDATA:DB IRAN
Addressing Modes
Register Addressing either source or
destination is one of CPU register
MOV R0,A
MOV
ADD
ADD
MOV
MOV
MOV
A,R7
A,R4
A,R7
DPTR,#25F5H
R5,DPL
R,DPH
Addressing Modes
Direct Mode specify data by its 8-bit
address
Usually for 30h-7Fh of RAM
Mov
Mov
Mov
Mov
a, 70h
R0,40h
56h,a
0D0h,a
Addressing Modes
Direct Mode play with R0-R7 by direct
address
MOV A,4
MOV A,R4
MOV A,7
MOV A,R7
MOV 7,2
MOV R7,R6
MOV R2,#5
MOV R2,5
;Put 5 in R2
;Put content of RAM at 5 in R2
Addressing Modes
Register Indirect the address of the source or
destination is specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0
mov r0, #0x3C
mov @r0, #3
Addressing Modes
Register Indexed Mode source or
destination address is the sum of the
base address and the
accumulator(Index)
Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr
;a M[4005]
Addressing Modes
Register Indexed Mode
continue
PC
1000
1002
1003
mov a, #5
movc a, @a + PC
Nop
;a M[1008]
Table Lookup
MOVC only can read internal code
memory
Acc Register
A register can be accessed by direct and register
mode
This 3 instruction has same function with different
code
0703 E500
0705 8500E0
0708 8500E0
mov a,00h
mov acc,00h
mov 0e0h,00h
mov a,r1
mov acc,r1
mov 0e0h,r1
SFRs Address
B always direct mode - except in MUL & DIV
0703 8500F0
0706 8500F0
mov b,00h
mov 0f0h,00h
0709 8CF0
070B 8CF0
mov b,r4
mov 0f0h,r4
mov p0,a
mov 80h,a
mov p0,p1
SFRs Address
All SFRs such as
(ACC, B, PCON, TMOD, PSW, P0~P3, )
Op code
add a,#3dh
;machine code=243d
Direct addressing
Op code
mov r3,0E8h
Direct address
;machine code=ABE8
Register addressing
Op code
070D
070E
070F
0710
0711
0712
0713
0714
0715
0716
0717
E8
E9
EA
ED
EF
2F
F8
F9
FA
FD
FD
n n n
mov
mov
mov
mov
mov
add
mov
mov
mov
mov
mov
a,r0
a,r1
a,r2
a,r5
a,r7
a,r7
r0,a
r1,a
r2,a
r5,a
r5,a
;E8
;E9
;EA
;ED
;Ef
=
=
=
=
=
1110
1110
1110
1110
1110
1000
1001
1010
1101
1111
070D
070D
070E
070F
0710
0711
0712
E7
93
83
E0
F0
F2
E3
i
; i = 0 or 1
mov
movc
movc
movx
movx
movx
movx
a,@r1
a,@a+dptr
a,@a+pc
a,@dptr
@dptr,a
@r0,a
a,@r1
Relative address
Op code
0700
0700
0702
0703
0704
0705
E106
00
00
00
00
Op code
A7-A0
1
2
3
4
5
6
7
8
org 0700h
ajmp next
nop
nop
nop
nop
next:
end
07FEh
;next=706h
Op code
A7-A0
020707
00
00
00
00
1
2
3
4
5
6
7
8
org 0700h
ajmp next
nop
nop
nop
nop
next:
end
;next=0707h
Stacks
push
pop
stack pointer
stack
Stack
Stack-oriented data transfer
Only one operand (direct addressing)
SP is other operand register indirect - implied
Stack (push,pop)
Therefore
Push
Push
Push
push
Push
Push
Push
Push
Push
Pop
Pop
Push
Pop
a
r0
r1
acc
psw
b
13h
0
1
7
8
0e0h
0f0h
;is
;is
;is
;is
;is
;is
invalid
invalid
invalid
correct
correct
correct
;acc
;b
Exchange Instructions
two way data transfer
XCH a, 30h
XCH a, R0
XCH a, @R0
XCHD a, R0
; a M[30]
; a R0
; a M[R0]
; exchange digit
a[7..4] a[3..0]
R0[7..4] R0[3..0]
Only 4 bits exchanged
Data Processing
Instructions
Arithmetic Instructions
Logic Instructions
Arithmetic Instructions
Add
Subtract
Increment
Decrement
Multiply
Divide
Decimal adjust
Arithmetic Instructions
Mnemonic
Description
ADD A, byte
ADDC A, byte
SUBB A, byte
INC A
increment A
INC byte
INC DPTR
DEC A
decrement accumulator
DEC byte
decrement byte
MUL AB
DIV AB
DA A
ADD Instructions
add a, byte
; a a + byte
addc a, byte
; a a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6, or
visa versa.
ADD Examples
mov a, #3Fh
add a, #D3h
0011 1111
1101 0011
0001 0010
C = 1
AC = 1
OV = 0
0111
1000
1111
complement:
0000 00 0
1111
0000
7F 127
80 -128
1111
FF -1
(positive 127)
0111 0011 (positive 115)
1111 0010 (overflow
cannot represent 242 in 8
bits 2s complement)
1000 1111
1101 0011
0110 0010
(negative 113)
(negative 45)
(overflow)
Addition Example
; Computes Z = X + Y
; Adds values at locations 78h and 79h and puts them in 7Ah
;-----------------------------------------------------------------X
equ
78h
Y
equ
79h
Z
equ
7Ah
;----------------------------------------------------------------org 00h
ljmp Main
;----------------------------------------------------------------org 100h
Main:
mov a, X
add a, Y
mov Z, a
end
Subtract
SUBB A, byte
Example:
SUBB A, #0x4F
;A A 4F C
Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.
Example:
Clr c
SUBB A, #0x4F
;A A 4F
increment A
INC byte
INC DPTR
DEC A
decrement accumulator
DEC byte
decrement byte
Multiply
When multiplying two 8-bit numbers, the size of the
maximum product is 16-bits
FF x FF = FE01
(255 x 255 = 65025)
MUL AB
; BA
A * B
Division
Integer Division
DIV AB
; divide A by B
A Quotient(A/B)
B Remainder(A/B)
OV - used to indicate a divide by zero condition.
C set to zero
Decimal Adjust
DA a
; decimal adjust a
Logic Instructions
Bitwise logic operations
(AND, OR, XOR, NOT)
Clear
Rotate
Swap
Logic instructions do NOT affect the flags in PSW
Bitwise Logic
ANL AND
ORL OR
XRL XOR
CPL Complement
Examples:
00001111
ANL 10101100
00001100
ORL
00001111
10101100
10101111
XRL
00001111
10101100
10100011
CPL
10101100
01010011
a, byte
direct, reg. indirect, reg,
immediate
byte, a
direct
byte, #constant
CPL Complement
ex:
cpl a
;PSW OR 00011000
RLC
RR
RRC
Carry
SWAP
clear
rotate
rotate
rotate
rotate
left
left through Carry
right
right through
A
byte
(direct mode)
Ri
(register mode)
@Ri
(register indirect mode)
Rotate
Rotate instructions operate only on a
RL a
Mov a,#0xF0 ; a 11110000
RR a ; a 11100001
RR a
Mov a,#0xF0 ; a 11110000
RR a ; a 01111000
RRC a
mov a, #0A9h
add a, #14h
; a A9
; a BD (10111101), C0
rrc a ; a 01011110, C1
RLC a
mov a, #3ch
setb c
; a 3ch(00111100)
; c 1
rlc a ; a 01111001, C1
a, #3 ; A 00000011 (3)
C
; C 0
a
; A 00000110 (6)
a
; A 00001100 (12)
a
; A 00000110 (6)
Swap
SWAP a
mov a, #72h
; a 27h
swap a
; a 27h
Shift/Mutliply Example
Program segment to multiply by 2
and add 1.
Unconditional Jumps
SJMP <rel addr>
Short jump,
relative address is 8-bit 2s complement number,
so jump can be up to 127 locations forward, or 128
locations back.
Long jump
Absolute jump to
anywhere within 2K block of program memory
JMP @A + DPTR
indexed jump
Long
Infinite Loops
Start: mov C, p3.7
mov p1.6, C
sjmp Start
Re-locatable Code
Memory specific NOT Re-locatable (machine
code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
ljmp Start
end
Jump table
Mov dptr,#jump_table
Mov a,#index_number
Rl a
Jmp @a+dptr
...
Jump_table: ajmp case0
ajmp case1
ajmp case2
ajmp case3
Conditional Jump
These instructions cause a jump to occur only if
a condition is true. Otherwise, program
execution continues with the next instruction.
loop: mov a, P1
jz loop
mov b, a
Conditional jumps
Mnemonic
Description
JZ <rel addr>
Jump if a = 0
Jump if a != 0
JC <rel addr>
Jump if C = 1
Jump if C != 1
Jump if bit = 1
Jump if bit != 1
&clear
else
send a 1 to LED
jz led_off
Setb P1.6
sjmp skipover
led_off: clr P1.6
mov A, P0
skipover:
Description
Iterative Loops
For A = 0 to 4 do
{}
clr a
loop: ...
...
inc a
cjne a, #4, loop
For A = 4 to 0 do
{}
mov R0, #4
loop: ...
...
djnz R0, loop
Iterative Loops(examples)
mov a,#50h
mov b,#00h
cjne a,#50h,next
mov b,#01h
next: nop
end
mov a,#0aah
mov b,#10h
Back1:mov r6,#50
Back2:cpl a
djnz r6,back2
djnz b,back1
end
mov a,#25h
mov r0,#10h
mov r2,#5
Again: mov @ro,a
inc r0
djnz r2,again
end
mov a,#0h
mov r4,#12h
Back: add a,#05
djnz r4,back
mov r5,a
end
; stack PC
; PC address 16 bit
Return
Return is also similar to a jump, but
Return instruction pops PC from stack to
get address to jump to
ret
; PC stack
Subroutines
call to the subroutine
Main:
...
acall sublabel
...
...
sublabel: ...
...
ret
the subroutine
Subroutine - Example
square:
push b
mov b,a
mul ab
pop b
ret
8 byte and 11 machine cycle
square: inc a
movc a,@a+pc
ret
table: db 0,1,4,9,16,25,36,49,64,81
db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3
end
reset service
main program
subroutine
data
Why Subroutines?
Subroutines allow us to have
"structured" assembly language
programs.
This is useful for breaking a large
design into manageable parts.
It saves code space when
subroutines can be called many
times in the same program.
example of delay
mov a,#0aah
Back1:mov p0,a
lcall delay1
cpl a
sjmp back1
Delay1:mov r0,#0ffh;1cycle
Here: djnz r0,here ;2cycle
ret
;2cycle
end
Delay=1+255*2+2=513 cycle
Delay2:
mov r6,#0ffh
back1: mov r7,#0ffh ;1cycle
Here: djnz r7,here ;2cycle
djnz r6,back1;2cycle
ret
;2cycle
end
Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
equ P1.6
org ooh
ljmp Main
org
Main:
Again:
Delay:
Loop1:
Loop0:
100h
clr
GREEN_LED
acall Delay
cpl
GREEN_LED
sjmp Again
reset service
mov
mov
R7, #02
R6, #00h
mov
R5, #00h
djnz
R5, $
djnz
R6, Loop0
djnz
R7, Loop1
ret
main program
subroutine
Example
; Move string from code memory to RAM
org 0
mov dptr,#string
mov r0,#10h
Loop1: clr a
movc a,@a+dptr
jz stop
mov @r0,a
inc dptr
inc r0
sjmp loop1
Stop:
sjmp stop
; on-chip code memory used for string
org 18h
String: db this is a string,0
end
Example
; p0:input p1:output
mov a,#0ffh
mov p0,a
back:
mov a,p0
mov p1,a
sjmp back
setb p1.2
mov a,#45h
;data
Again:
jnb p1.2,again ;wait for data
request
mov p0,a
;enable strobe
setb p2.3
clr p2.3
Example
; duty cycle 50%
back: cpl p1.2
acall delay
sjmp back
back:
setb p1.2
acall delay
Clr p1.2
acall delay
sjmp back
Example
; duty cycle 66%
back: setb p1.2
acall delay
acall delay
Clr p1.2
acall delay
sjmp back
8051 timer
Interrupts
Program Execution
mov a, #2
mov b, #16
mul ab
mov R0, a
mov R1, b
mov a, #12
mov b, #20
mul ab
add a, R0
mov R0, a
mov a, R1
addc a, b
mov R1, a
end
interrupt
ISR: inc r7
mov a,r7
jnz NEXT
cpl P1.6
NEXT: reti
return
Interrupt Sources
Original 8051 has 5 sources of
interrupts
Timer 0 overflow
Timer 1 overflow
External Interrupt 0
External Interrupt 1
Serial Port events (buffer full, buffer empty, etc)
Interrupt Process
If interrupt event occurs AND interrupt flag for that
event is enabled, AND interrupts are enabled,
then:
1. Current PC is pushed on stack.
2. Program execution continues at the interrupt
vector address for that interrupt.
3. When a RETI instruction is encountered, the PC
is popped from the stack and program
execution resumes where it left off.
Interrupt Priorities
What if two interrupt sources
interrupt at the same time?
The interrupt with the highest
PRIORITY gets serviced first.
All interrupts have a default priority
order.
Priority can also be set to high or
low.
Interrupt SFRs
Interrupt Vectors
Each interrupt has a specific place in code memory
where program execution (interrupt service routine)
begins.
External Interrupt 0: 0003h
Timer 0 overflow:
000Bh
External Interrupt 1: 0013h
Timer 1 overflow:
001Bh
Serial :
0023h
Timer 2 overflow(8052+) 002bh
Interrupt Vectors
To avoid overlapping Interrupt Service routines, it
is common to put JUMP instructions at the vector
address. This is similar to the reset vector.
org 009B
ljmp EX7ISR
cseg at 0x100
Main: ...
;
...
EX7ISR:...
;
...
;
reti
;
; at EX7 vector
; at Main program
Main program
Interrupt service routine
Can go after main program
and subroutines.