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pn diode
p
No control
MOSFET
n
I
pp
TRANSISTORS
n
BJT
I
pp
I
V
Metal-Semiconductor Field
Effect Transistors
MOSFETs
MOSFET fabrication
1. p-type substrate
2. Thermal oxidation
3. Poly-Si deposition
4. Lithography and Ohmic
contact window opening
5. Donor implantation and
thermal anneal.
5. Lithography and metal
deposition.
5. Back contact.
Drain: D
S, B: normally grounded
Bulk contact: B
n+
SiO2
NO CURRENT
n+
p-Si
CONTROL
The voltage on the gate can create a
conduction path between source and
drain and control the amplitude of the
current that is flowing.
n-channel MOSFET
Enhancement mode:
no conduction when no gate voltage applied
p-Si substrate
n+ Ohmic contacts
source, drain contacts
SiO2 oxide insulator
gate contact
bulk contact grounded with S
Energy band
diagram from
GB
Energy band
diagram
from S D
p-Si
Assume SiO2
perfect insulator
current I = 0A
Capacitive effects
Electric field effect
m= s
G
n+-Si
D
n+-Si
p-Si
B
nMOS
em
oxide
Ec
semiconductor
Evac
es
eSi
Ec
EFs
Ev
EFm
1) Workfunction: m= s
2) Electron affinity in
oxide
e SiO2 = Evac-EcSiO2
2) p-type semiconductor
3) No e- transfer
Ev
p-Si
m= s
G
n+-Si
n+-Si
Ecox
p-Si
EcSi
B
nMOS
EFSi
EvSi
EFSi
Flatband condition
Evox
tox
+
+
E
Ecox
EFm
Evox
h+
p-Si
tox
accumulation of holes
+
+
Ecox
EFm
Evox
NA-
tox wp
Depletion of holes
p-Si
++
++
THRESHOLD VOLTAGE
--E
Ecox
attraction of
electrons
EcSi
EFSi
EvSi
EFm
Evox
e- NA-
-- -- -- tox wpmax
Depletion of holes
p-Si
THRESHOLD VOLTAGE
---
++
++
Ecox
EcSi
ns
eVth
EFm
Evox
p EFSi
EvSi
MOS-capacitor
Capacitance varies with gate voltage
C
accumulation
Cmax = Cox A
Oxide capacitance
depletion
Vth
1/Cmin = 1/(Cox A)+1/(Cdepl A)
Depletion capacitance
m=s
VGSV>0
GS
Inversion region
Depletion region
hhh+++
O n
Ecox
p-Si
EF
Evs
Evox
on p-Si
ddeplmax
Ecs
E
EFm
Fm
EFm
EFm
Inversion
Revision
equilibrium
Depleting
> V th p-Si
V
GS =
Inversion
Onset
of inversion
VGS
Energy band
diagram
from S D
0V
G
0V
D
channel
n+
eV0
n+
Ec
EF
Ev
Potential barrier between supply of electrons from source into channel
0V
G
VDS>0V
D
channel
E
eV0
n+
p
n+
Potential barrier between supply of electrons from source into channel
stops diffusion of e- from source into channel IDS = 0V
S
G
channel
channel
channel
D
0V
0V
source
G ox
p-Si
Ec
EF
Ev
G ox
channel
p-Si
Ec
EF
eVGS
EF
Ev
Threshold!
VGS=Vth
G ox
channel
p-Si
Ec
E
EFF
e VGS
EF
Ev
Full of electrons
channel
n+
p n
n+
Ec
EF
Ev
Potential barrier between supply of electrons from source into channel
Potential barrier between supply of electrons from source into channel
is lowered, thus electrons from source will not be blocked if
attracted by drain
channel
n+
n+
Ec
EF
Derivation of currents in
MOSFETs
dn( x)
J n ( x) e n n( x)E ( x) eDn
dx
dp( x)
J p ( x) e p p ( x)E ( x) eD p
dx
VGSVth
VDS 0
dn( x)
dx
dp ( x)
J p ( x) e p p ( x)E ( x) eD p
dx
J n ( x) e n n( x)E ( x) eDn
SD
Drift eDrift e-
Diffusion e
+
ECS n
EFS
EVS
Drift h
GB
@S
GB
@D
EFS
EFD
n+ ECD
EFD
+
EVD
Diffusion h+
Diffusion h+ Drift h+
nsD
nsS
Diffusion
eEV EF
EC
EV EF
EC
Derivation of currents in
MOSFETs
Current in single carrier type layer under
electric field: drift current
I e n( x) E ( x) A
dV ( x)
I en( x)
A
dx
Q
Take VDS = 0
Apply VGS Vth
VDS
Remember:
S
VGS>Vth
Qn
Cox
Qn = charge/unit area
Cox V
Cox = 0 ox/tox
Qn = CV
Which V?
Assume: @ VGS = Vth : Qn = 0
then:
Qn = -Cox (VGS Vth)
Charge in the channel under
the gate per gate area
Inversion layer
Vx(x)
VDS
Charge in channel
Qn = -Cox (VGS - Vx(x) - Vth)
Vx(x)
VDS
VG >Vth
VS =0
VS
VD >0
VS
VG
aD
aS
VS
Charge:
Inversion layer
width:
VG
QnS=-Cox(VGS-Vth)
aS = a0 QnS
Channel region
VD
VD
VD
QnD=-Cox(VGD-Vth)
QnD=-Cox((VGS VDS)-Vth)
Since VGS VDS<VGS
QnD< QnS aD < aS
VG >Vth
VG
VG
Channel region
VS =0
VS
VD >0
S
VS
VD
aS
VS
Charge:
Inversion layer
width:
QnS=-Cox(VGS-Vth)
aS = a0 QnS
VD
VD
Q
QnnDD=-C
=-Coxox(V
((VGDGS-V
V
th)DS)-Vth)
QnD=-Cox((VGS (VGS -Vth))-Vth)
QnD=0 aD =0
Current in channel
Drift current:
I = e nn(x) e E A
constant
area
-dVx/dx
graphs in books
Current in channel
Drift current:
I = e nn(x) e E A
tox
ox
S
a(x)
channel
x
Current in channel
Drift current:
I = e nn(x) e E A
tox
L
a(x)
channel
x
Current in channel
Drift current:
I = e nn(x) e E A
n(x)
#carriers/volume (=W L a)
tox
n(x) = Qn(x)/(a(x) e)
n(x) = -Cox (VGS - Vx(x) Vth)/(a(x) e)
Current in channel
A
I = -e Cox (VGS - Vx(x) Vth) e E A/(a(x)
e)
A: area of current flow
A = a(x) W
tox
L
Current
I = Cox (VGS V(x) Vth) W e dVx/dx
0L I dx = Cox W e 0VDS (VGS Vx(x) Vth) dVx
I = Cox e (W /L) [(VGS Vth) VDS- VDS2/2]
Electron
Oxide capacitance mobility
per area
in
channel
Threshold voltage
Length of
channel
Width of channel
Current-voltage characteristics
0< VGS Vth
VDS < VGS Vth
VGS
VDS
R(VGS)
Triode region:
voltage controlled resistance
Vy VGS
Vth
Pinch-off
I = Cox W e /2L (VGS Vth)2
Saturation region:
voltage controlled current source
I DS
2
n C oxWg
VDS
Lg
2
n C oxWg
Lg
Onset of saturation
Triode region
Linear
Resistor behaviour
n C oxWg
2 Lg
VGS Vth 2
Saturation region
Constant
Current source
VGS
VDS
in triode region
IDS
IDS
VDS1
VGS
VDS
Vth
VGS
in saturation region
IDS
IDS
VGS
VDS
Vth
VGS
VGS
VDS
How well does the gate control the current?
gm
I
sat
DS
dI DS
dVGS
Ro
nC oxWg
VGS Vth 2
2 Lg
g msat
nC oxWg
VGS Vth
Lg
gmvgs
Transconductance, gm
dI DS
Ro
dVDS
no longer inverted
depleted
channel
n+
V0-Vsi
n+
Ec
Ec
Ev
Ev
EF
EF
Large part of the VDS will be dropped across the channel-drain depletion region = reverse
biased pn diode.
If VDS is increased, most of the extra voltage will be dropped across the channel-drain
depletion region.
channel
n+
n+
V0-Vsi
Ec
EF
Ev
Negligible change in slope of potential energy Ec in channel
No change in source-channel barrier (controls carrier supply)
Thus current remains constant
e(V0+Vr)
Ec
EF
Hole energy
Any extra is
made available
by source and
is controlled by
the source
channel
potential barrier
Electron energy
Channel
Ev
Hole diffusion
Hole drift
TCAD simulations
Numerical solution of the transport equations
D
Vx(x)
saturation
channel
linear
S
VGS
VGS
I 1/L
L L-L
I 1/(L-L)
VDS
VDS
L
L
Channel length L
has decreased by L
VG >Vth
VG
VG
Channel region
VS =0
VS
VD >0
S
VS
L
aS
VS
Charge:
Inversion layer
width:
VD
VD
L
L
VD
QnS=-Cox(VGS-Vth)
aS = a0 QnS
>0
G
p-channel
pMOS
>0
D
n
0
S
+
h
p
<0
G
Vth>0
Vth<0
Carriers in channel: e-
<0
D
p
Carriers in channel: h+
S
S
Depletion mode
VDS =0
VDS =0
VGS=0
G
D
D
VGS =0
G
D
D
No channel
S
S
Channel exists
IDS
VGS VGS
5 2
4
3
2
1
0
-1
-2
VDS
VDS1
Vth
Vth
VDS1
VGS
CMOS
Vth<0V
IDS
VGS
VD>Vth
pMOS
in
out
vout
vin
nMOS
vin
vout
VD
IDS
VGS
Vth>0V
VD
Conclusions
A MOSFET is a majority carrier device.
The width of the conducting channel and thus the
amount of carriers in the channel is determined by
the gate voltage.
Current is determined by drift through a channel.
The current is inversely proportional to the length
of the gate.
The transconductance is a measure of how good
the gate controls the current through the channel.
Different modes of operation exist dependent on
carrier type and inversion layer width without gate
bias.