Microoperations mostly encounter in registers are of 4 types

Register Transfer microoperation.

Arithmetic microoperation.
Logical microoperation.
Shift microoperation.

Arithmetic Microoperation
R3 R1+R2
is a simple add
microoperation
where the content of
R1 and R2 are added
and the result is
stored in register R3

Binary Adder - Subtractor

Binary
Incrementer

Logical Micro Operations

These operations are performed bit
by bit.
For Ex :Exclusive-OR on Registers R1
and R2 is symbolized as follows

There are 16 different logical operations that can be performed

on the 2 binary variables.

10

11

12

Hardware implementation for

Logical Micro operations

13

Some of the Applications of Logical

Operations

14

Cont.

15

Shift Micro operations

Shift Micro Operations are used for serial transfer of data .
The Contents of Registers can be shift to left or Right
The first flip flop receives information from the serial input.
During the shift left operation the serial input transfer a bit of
data into right most position
During the shift right operation the serial input transfer a bit of
data into left most position
The Information transferred through the input determines the
type of shift.

Basically there are 3 types of shifts

Logical shift
Circular shift
Arithmetic Shift

16

Types of Shift Operations

17

18

Hardware Implementation

When the selected input is 0

i.e., s=0 the shift is right shift
When the selected input is 1
i.e., s=1 the shift is left shift.

19

Arithmetic Logic Shift Unit

Instead of having individual registers performing the micro operations directly

Computer system employ a number of Register storage connected to the comm
Operation unit called ALU
ALU which performs arithmetic and logical operations on the contents of the
specified registers
ALU perform operations and the result is send to the destination register.

20

21

Instruction Codes
Computer Instructions is a binary code that
specifies a sequence of micro operations to the
computer.
Instruction Codes together with data are stored
in memory.
The computer reads the instructions from the
memory and place in the control register. The
control then interprets the binary code of the
instruction and then executes it by issuing a
sequence of micro operations.
Every computer has its own set of instruction set.
22

Cont
An instruction code is a group of bits that instructs
the computer to perform specific operation.
It is usually divided into parts. Each part has its
own interpretation(meaning).
The most basic part of instruction code is OPCODE
The operation code of an instruction are group of
bits which specifies operation to be performed.
(ADD,SUB,MUL,DIV)
The number of bits in op code depends up on the
number of operations available in the computer.
23

Stored Program
Organization

24

Accumulator

25

Direct and Indirect

Addressing

26

Direct and Indirect Addressing

27

Cont

28

Cont

29

Computer Registers

30

Program Counter

To read an instruction, the content of PC is taken as the address for

memory and a memory read cycle is initiated. PC is then incremented
by one, so it holds the address
of the next instruction in sequence.

31

Basic Computer Registers and

Memory

32

33

Common Bus System

DR, AC , IR, and TR are 16 bit Registers .
AR and PC are 12 bit Registers Since they hold only addresses.
OUTR and INPR are 8 bit Registers since they hold single character
only.
When ever 16 bit registers communicated with 16 bit common
bus it uses total 16 bits for communication.
When ever these AC (12)and PC(12), OUTR(8) and INPR(8)
communicate with the 16 bit bus they used only least significant
bit that they can.
OUTR can only receive information from the bus. OUTR receives a
character from AC and delivers it to an output device. There is no
transfer from OUTR to any of the other registers.
INPR receives a character from an input device which is then
transferred to AC.

34

Common Bus System

The input data and output data of the memory are connected to the
common bus, but the memory address is connected to AR.
Therefore, AR must always be used to specify a memory address.
The 16 lines of the common bus receive information from six registers
and the memory unit. The bus lines are connected to the inputs of six
registers and the memory. Five registers have three control inputs: LD
(load), INR (increment), and CLR (clear)
The 16 inputs of AC come from an adder and logic circuit. This circuit
has three sets of inputs. One set of 16-bit inputs come from the
outputs of AC . They are used to implement register microoperations
such as complement AC and shift AC . Another set of 16-bit inputs
come from the data register DR . The inputs from DR and AC are
used for arithmetic and logic microoperations, suc as add DR to AC or
AND DR to AC . The result of an addition is transferred to AC and the
end carry-out of the addition is transferred to flip-flop E (extended AC
bit). A third set of 8-bit inputs come from the input register INPR .
35

Cont
Note: that the content of any register can be applied onto the bus
and an
operation can be performed in the adder and logic circuit during the
same clock
cycle. The clock transition at the end of the cycle transfers the
content of the
bus into the designated destination register and the output of the
adder and
logic circuit into AC . For example, the two microoperations

36

Computer
Instructions(Indetail)
Basic Computer
has three instruction formats.
Memory Reference.(Direct & Indirect Addressing)
Register Reference.
Input and Output Reference.
The operation code (opcode) part of the instruction contains three bits
Remaining 13 Bits are used to Differentiate the Instructions.
I bit Is used to indicate whether the instruction is Direct
Reference or Indirect Reference
Register Reference Instructions can be identified by 111 in the opcode
and I=0;
Input and output Reference will be differentiate by 111 in the opcode
and I=1;
A register-reference instruction specifies an operation on or a test of the
AC register. An operand from memory is not needed; therefore, the other
12 bits are used to specify the operation or test to be executed.
Similarly, an input-output instruction remaining 12 bits are used to
specify the type of input-output operation or test performed.
The type of instruction is recognized by the computer control from the
four bits in positions 12 through 15 of the instruction. If the three opcode
37
bits in positions 12 though 14 are not equal to Ill, the instruction is a

Computer Instructions

38

39

Instruction Set
Completeness
1. Arithmetic, logical, and shift instructions
2. Instructions for moving information to and from memory and
processor
registers
3. Program control instructions together with instructions that
check
status conditions
4. Input and output instructions

40

Determine the Type Of

Instruction

41

Instruction Cycle

e program in the computer is executed by going through a cycle for each instruc
ch Instruction cycle is subdivided into a sequence of sub-cycles or phases.
consists of following steps
Fetch the Instruction.
Decode the instruction.
Get the effective address if it is in indirect addressing.
Execute the instruction.
After Completion of the step 4 the control goes back to the step 1 to fetch ,
decode, and execute the next instruction Unless HALT instruction is encountered.

42

Fetch and Decode

Initially, the PC is loaded with the address of the first instruction
in the program.
Make SC to 0 or CLEAR SC providing Decoding timing signal to 0.
After each clock pulse SC is incremented. So that timing signals
go to T0,T1,T2.
Let Us see the Fetch and Decode cycles at timing T0,T1,T2
in RTL.

43

44

45

Register Transfer for the Fetch Phase

46

Determine the Type Of

Instruction

47

Cont

Here in Memory Reference Instruction the instruction will be

continued with the next timing cycle T4. where as the Register
reference instructions or input and output instructions are
completed with T3 cycle since the operation will complete at T3
cycle. In RRI and IORI sc=0 after T3 and Fetch for the next
instruction.
48

Memory Reference
Instructions.

49

AND to AC

The control function for this instruction uses the operation decoder D0
since this output of the decoder is active when the instruction has an AND
operation whose binary code value is 000. Two timing signals are needed
to execute the instruction. The clock transition associated with timing
signal T4 transfers the operand from memory into DR . The clock
transition associated with the next timing signal T5 transfers to AC the
result of the AND logic operation between the contents of DR and AC . The
same clock transition clears SC to 0, transferring control to timing signal
T0 to start a new instruction cycle

50

ADD to AC

The same two timing signals, T, and T5, are used again but with
operation decoder D1 instead of D0, which was used for the AND
instruction. After the instruction is fetched from memory and decoded,
only one output of the operation decoder will be active, and that output
determines the sequence of micro operations that the control follows
during the execution of a memory-reference instruction.

51

STA to AC
This instruction will save the content of AC into the
memory word specified by the effective address.
Since the output of the AC is connected to the
common bus the data is transferred in one micro
operation.

52

LDA to AC

This instruction transfers the memory word specified by the effective

address to AC.
Looking back there is no direct connection between the Common bus and
the AC register
so., the Data or memory word specified by the AR will be loaded into the
AC from DR.
(First the Data is loaded into the DR and then transferred to the AC by
Logic and Shift Circuit)
Therefore it is need to read the memory word into DR first and then
transfer the content into AC.
53

BUN (Branching
UNconditional)

Generally PC holds the address of the next Instruction to be executed.

PC is incremented every time to get the next instruction .
When every an uncondition branching instruction is executed the AR
Contains the address of the next instruction to be executed.so we
need to bring back that to PC counter and the set SC=0 transfer
control to T0.

54

BSA(Branch and Save return

Address)

55

ISZ Increment and skip if

Zero

56

Control Flow in Memory Reference

Instructions.

57

Register Reference
Instruction
Register Reference instructions can be identified by the control
when D7=1 and I=0.
In this type of Instructions BITS 0-11 are used to specify one of
the 12 instructions IR(0-11). They are transferred to AR at timing
T2.
For example, the instruction CLA has the hexadecimal code 7800
which gives the binary equivalent 0111 1000 0000 0000. The first
bit is a zero and is equivalent to I'. The next three bits constitute the
operation code and are recognized from decoder output D7
Bit 11 in IR is I and is recognized from B11
The control function that initiates the micro operation for this
instruction
is D7I 'T3B11 = rB11

58

Register Reference Instruction Exection

This can be memorized as follows.

59

INPUT OUPUT and

INTERRUPT.

60

INPUT AND OUTPUT INSTRUCTIONS.

In the Next slide we will compare it to the Register

Reference Instruction.
61

Interrupts.
Interrupts
are
arise
due
to
differences in the data transfer rate
between the I/O devices and the
speed at which processor executes
the
programs(Speed
of
the
Processor).
An alternative to the programmed
controlled procedure is to let the
external
device inform the
computer when it is ready for the
transfer. In the meantime the
computer can be busy with other
tasks
An interrupt flip-flop R is included in
the computer. When R = 0, the
computer goes through an
instruction cycle.During the execute
phase of the instruction cycle lEN is
checked by the control. If it is 0, it
indicates that the programmer does
not want to use the interrupt, so
control continues with the next
instruction cycle.

If lEN is 1, control checks the

flag bits. If both flags are 0, it
indicates that neither the
input nor the output registers
are ready for transfer of
information. In this case,
control continues with the
next instruction cycle. If
either flag is set to 1 while
lEN = 1, flip-flop R is set to 1.
At the end of the execute
phase, control checks the
value of R, and if it is equal to
1, it goes to an interrupt cycle
instead of an instruction
cycle.

Finally RTL statement for the

Interrupt cycle is as follows.
62

Cont

63

CPU General Register Topics

In most of the application Most of the
time is wasting for Memory accessing it is
more convenient to have number of
process register to have so that the time
will be reduced.

A bus organization with 7 registers and

CPUs are connected in the following
block diagram. In that the output of each
register is connected to the 2 multiplexers
to form 2 common BUS A and B. These A
and B forms the input to the ALU
The operation selected in the ALU deter
mines the arithmetic or logic micro
operation that is to be performed. The
result of the micro operation is available
for output data and also goes into the
inputs of all the registers. The register
that receives the information from the
output bus is selected by a decoder.

64

Register set with Common ALU

65

Control Inputs for selected outputs.

Control Word is a 14 bit binary selection input in the control
unit . CW is divided
into 4 parts or fields 3 fields are 3 bits each and 4th field is 5bits.
SELA

SELB

SELD

OPR

66

Encoding for ALU operations and

example.

67

68

69

Reverse Polish Notation

A stack organization is very
effective for arithmetic
evaluation. Common
expression is difficult to
evaluate thats why uses
reverse polish notations.

Consider the Arithmetic

Expression

70

Instruction Formats

Operations specified by computer

instructions are executed on some
data stored in memory or processor
registers. Operands residing in
memory are specified by their
memory address. Operands
residing in processor registers are
specified with a register address. A
register address is a binary number
of kbits that defines one of 'l!'
registers in the CPU. Thus a CPU
with 16 processorregisters RO

Computers may have Instructions of

several different lengths containing
varying number of addresses. The
number of address fields in the
instruction format of a computer
depends on the internal organization
of its registers. Most
computers fall into one of three types
of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization

through R15 will have a register address

field of four bits. The
binary number 0101, for example, will
designate register RS

71

Evaluating the X=(A+B)*(C+D)in all addressing

modes

RISC INSTRUCTIONS

72

Addressing Modes

73

Addressing Modes

74

Addressing Modes

75

Addressing Modes

76

Data Transfer and Manipulation

77

78

Program Control

79