56 views

Original Title: Differential and Multistage Amplifiers

Uploaded by Shino Joseph

- chapter 3.pptx
- Stereo Amplifier Assembly Manual
- ECX 4150 Assignment 1 - 2016
- LIC-II-ECE-NOTES
- B-stad_CH_05.pdf
- 1
- Cs amplifier
- Report 1 Electro2
- Chapter 5 - ele232_feb11 [Compatibility Mode] (1).pdf
- ELECS-LAB-1
- Electronic Circuits - I Lecture Notes for B.E. (ECE) (Low Resolution)
- Electronics Lab 15
- Chen - VLSI Handbook [CRC Press 1999]-CHP20
- Eeeb273 1011s1 Mt Qna
- DCIO Paper
- DC Baising and Operation of JFET Amplifier
- 2-A Novel Circuit Model
- bsnl mixed sample papersMixed 2
- lect07
- Audio Amp DNA

You are on page 1of 85

The most widely used circuit building block in analog integrated

circuits.

Use BJTs, MOSFETS and MESFETs (metal semiconductor FET

read 5.12 Gallium Arsenide-GaAs Device).

widely used circuit building blocks. The input

stage of every op amp is a differential amplifier

Basic Characteristics

Two matched transistors with emitters

shorted together and connected to a current

source

Devices must always be in active mode

Amplifies the difference between the two

input voltages, but there is also a common

mode amplification in the non-ideal case

Lets first understand how this circuit works.

vCM, called the common mode voltage

equal currents flow through Q1 and Q2

emitter voltages equal and at vCM-0.7 in order for the

devices to be in active mode

collector currents are equal and so collector voltages are

also equal for equal load resistors

difference between collector voltages = 0

What happens when we vary vCM?

As long as devices in active mode, equal currents flow

through Q1 and Q2

Note: current through Q1 and Q2 always add up to I,

current through the current source

So, collector voltages do not change and difference is still

zero.

Differential pair circuits thus reject common mode signals

All current flows through Q1

No current flows through Q2

Emitter voltage at 0.3V and Q2s EBJ not FB

vC1 = VCC-IRC

vC2 = VCC

All current flows through Q2

No current flows through Q1

Emitter voltage at -0.7V and Q1s EBJ not FB

vC2 = VCC-aIRC

vC1 = VCC

Causes a small positive DI to flow in Q1

Requires small negative DI in Q2

since IE1+IE2 = I

Can be used as a linear amplifier for small

signals (DI is a function of vi)

Differential pair responds to differences in the

input voltage

Can entirely steer current from one side of

the diff pair to the other with a relatively

small voltage

Lets now take a quantitative look at the largesignal operation of the differential pair

Large-Signal Operation

First look at the emitter currents when the emitters are tied together

v B 1 VE

VT

IS

IS

i E1 e

iE 2 e

iE1

iE1 iE 2

i E1

e

iE 2

v B 2 VE

VT

iE 2

iE 1 i E 2

1

1 e

v B 2 v B1

VT

vB1 vB 2

VT

1

1 e

vB1 vB 2

VT

iE1 iE 2 I

Given the exponential relationship, small differences in vB1,2 can cause all of the current to flow through

E1

vB 2 vB1

E2

one side

vB1 vB 2

VT

V

1 e

1 e

Notice vB1-vB2 ~= 4VT enough to switch all of current from one side to the other

For small-signal analysis, we are interested in the region we can approximate to be

linear

small-signal condition: vB1-vB2 < VT/2

Small-Signal Operation

differential signal vd is applied

vB1 vB 2 vd

iC1

1 e

multiply top

and bottom

by

vd

2VT

Ie

iC1

e

vd

2VT

vd

VT

vd

2VT

vd

2VT

two terms

iC1

I 1 vd 2VT

I I vd

iC 2

I I vd

2 2VT 2

I vd

ic

2VT 2

ic g m vd 2

gm

I C I 2

VT

VT

For small differential input signals, vd << 2VT, the collector currents are

vd

iC1 I C g m

2

vC1 VCC

vd

I C RC g m RC

2

iC 2

vd

IC gm

2

vC 2 VCC

vd

I C RC g m RC

2

vc1 vc 2

Ad

g m RC

vd

We can break apart the differential pair circuit into two half circuits which

then looks like two common emitter circuits driven by +vd/2 and vd/2

circuit, but must remember

parameters r,gm, and ro are biased at I/2

input signal to the differential half circuit is vd/2

voltage gain of the differential amplifier (output taken

differentially) is equal to the voltage gain of the half circuit

vc1

gmv

vd/2

vc1

Ad

g m RC ro

vd 2

RC

Common-Mode Gain

vCM, the incremental resistance of the bias current effects circuit

operation and results in some gain (assumed to be 0 when R

was infinite)

vC1 vCM

RC

RC

vCM

2 R re

2R

vC 2 vCM

RC

2R

If the output is taken differentially, the output is zero since both sides move

together. However, if taken of the single circuit, the common-mode gain is finite

Acm

RC

2R

Ad g m RC

CMRR

Ad

1

gm R

Acm 2

CMRR 20 log10

Ad

Acm

components: common mode (vCM) and differential(vd)

vCM

v1 v2

vd v1 v2

v1 v2

vo Ad v1 v2 Acm

2

Connection to RC not

essential to the operation

Essential that Q1

and Q2 never enter

saturation

Use CD

Implemented by a

transistor circuit

Common voltage

I/2

vE = vCM-VBE

vC1 = VCC ( ) I RC

vC2 = VCC ( ) I RC

vC1 vC2 = ?

Vary vCM (what happens?)

Rejects common-mode

vB1 = +1

Q1

Q2

vE = 0.3

Keeps Q2 off

vC1 = VCC - I RC

vC2 = VCC

To that of (b)

Exercise 6.1

5 0.7

1

4.3

vC2 5 4.3 1

vC1 5

vE 0.7

vC2 0.7

Equations

iE1

( vB1 vE)

iE1

iE2

IS

IS

iE1 iE2

VT

( vB2 vE)

iE1

VT

iE2

( vB2 vB1)

VT

1 e

( vB1 vB2)

iE1 iE2

VT

iE2

iE1 iE2

( vB1 vB2)

1 e

VT

1

iE1

The collector

currents

can be obtained by

multiplying the

emitter currents by

Alfa, which is ver

close to unity

( vB2 vB1)

VT

1 e

iE2

( vB1 vB2)

1 e

VT

Relatively small

difference voltage vB1

vB2 will cause the

current I to flow almost

entirely in one of the two

transistors.

4.VT (~100mV) is

sufficient to switch the

current to one side of the

pair.

Small-Signal Operation

The Collector Currents When vd is applied

vd

iC1

vB1 vB2

I

iC2

vBQ1

I vd

2

2 VT 2

VBE

vd

vd

I vd

2

2 VT 2

vd

VT

I e

iC1

ic

VBE

e

I

vd

2

gm

2 VT

vd

vd

iC1

vBQ2

2 VT

I

1 e

vd

VT

1 e

iC2

Multiplying by

vd

2 VT

2 VT

Assuming vd<<2VT

IC

VT

VT

iC1

I 1

vd

2 VT

vd

2 VT

vd

2 VT

An Alternative Viewpoint

Assume I to be ideal its incremental resistance will be infinite and vd appears across a total

resistance 2.re.

re

VT

VT

IE

vd

ie

2 re

ic

ie

vd

2 re

gm

vd

2

determining the signal currents

in a differential amplifier

excited by a differential voltage

signal vd; dc quantities are not

shown.

ie

vd

2 re 2 RE

A differential amplifier with emitter resistances. Only signal quantities are shown (on color).

vd

ib

Rid

ie

2 re

vd

ib

1 2re

2 r

This is the resistance-reflection rule; the resistance seen between the two bases is

equal to the total resistance in the emitter circuit multiplied by the beta+1

Rid

1 ( 2 re 2 RE)

iC1

IC gm

vd

2

vC1

( VCC IC RC) gm RC

vC2

( VCC IC RC) gm RC

Ad

Ad

vc1 vc2

vd

IC gm

iC2

vd

2

vd

2

gm RC

( 2RC)

( 2 re 2 RE)

RC

re RE

ratio of the total resistance in the

collector circuit (2RC) to the total

resistance in the emitter circuit

(2re+2RE)

vd

2

IC

I

2

Differential amplifier fed in a

complementary manner (pushpull or balanced)

Base of Q1 raised

Based of Q2 lowered

Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). This

equivalence applies only for differential input signals. Either of the two common-emitter

amplifiers in (b) can be used to evaluate the differential gain, input differential resistance,

frequency response, and so on, of the differential amplifier.

RC ro

Ad gm

RC ro

Common-Mode Gain

Assuming symmetry

Common-mode

half-circuits

vc1

vCM

vc2

vCM

Acm

vo

RC RC

2 R RC

Ad ( v1 v2) Acm

vCM

v1 v2

v1 v2

2 R re

vCM

RC

2 R

RC

2 R

Acm and the differential gain Ad

We can define CMRR

Acm

Assuming non-symmetry

RC

CMRR

RC

2 R

Ad

Acm

Ad

1

2

gm RC

CMRR gm R

Ricm

r

ro

vCM

vCM

2 . Ricm

Ricm =

Since the input common-mode resistance

is usually very large, its value will be

affected by the transistor resistances

R0 and r

Example 6.3

I 1

VCC 15

RC 10

vB2( t) 5 0.005 sin 2 1000 t

vBE 0.7

at 1mA

a)

VBE 0.7 0.025 ln

0.5

vE 5 VBE

VBE 0.683

vE 4.317

b)

gm

IC

gm 20

VT

c)

iC1( t) 0.5 gm 0.005 sin 2 1000 t

0.6

iC1( t ) 0.5

iC2( t )

0.4

0.3

0.001

0.002

0.003

t

0.004

0.005

d)

vC1( t ) ( VCC IC RC) 0.1 RC sin 2 1000 t

vC2( t ) ( VCC IC RC) 0.1 RC sin 2 1000 t

11

vC1( t )

vC2( t )

10

0.001

0.002

0.003

0.004

0.005

0.003

0.004

0.005

e)

vC2( t ) vC1( t )

0.001

0.002

t

Input Offset Voltage

Exercise 6.4

100

Delta_RC 0.02

Delta_IS 0.1

Delta_ 0.1

I 100

2

Delta_RC

VOS VT

RC

IB

Delta_

VOS 2.55

IB 0.495

2 1

IOS IB

Delta_IS

IS

IOS 4.95 10

50nA

Many resistors, transistors and capacitors makes impossible to use

conventional biasing methods

Biasing in IC is based on the use of constant-current sources

The Diode-Connected Transistor

Shorting the base and the collector of a BJT results in a twoterminal device having an I-v characteristic identical ot the

iE-vBE of the BJT.

i

i

1

active mode operation) the current I divides between base

and collector according to the value of the BJT Beta.

Thus, the BJT still operates as a transistor in the active mode.

This is the reason the I-v characteristics of the resulting

diode is identical to the iE-vBE relationship of the BJT

Exercise 6.5

R incremental = r // (1/gm) // ro

1

gm

1

r

Rinc

r

r

ro

gm

1

gm

1

gm

r

r

ro

ro

ro

re ro

re ro

re

Rinc

25

0.5

Rinc 50

current mirror have a gain error

1%, 0.1 %

Io

current diverted from reference

current IREF

IO

IE

IO

IREF

IREF

IE

IO

1

1

I REF

V O V EE V BE

VA

Exercise 6.6

VEE 5

Rout

VBE 0.7

IO

at

IREF

100

Rout 1 10

IREF

at

VO

VB

IREF

1

IREF 0.001

VA

ro

Rout

100

VO VEE VBE

VO 4.3

IO 9.804 10

VO 5

IO5 IO

5 ( 4.3)

Rout

IO5 1.073 10

IREF

Io

VCC

I REF

V CC V BE

R

Dependence of Io and Vo, the output

current Io will be equal IREF

VBE

Exercise 6.7

IO

IREF 0.001

IREF

VCC 5

at

VCC VBE

IREF

VO 3

100

R 4.3 10

IREF

1 2

VA 50

ro

IO

VBE 0.7

VO VBE

ro

VA

IREF

ro 5 10

IO 1.026 10

Current-Steering Circuits

I REF

V CC V EE V EB1 V BE2

R

IC Circuits

2 power supplies

IREF is generated in the branch of

the diode-connected transistor Q1,

resistor R, and the diode-connected

transistor Q2.

Exercise 6.9

1 - The MOS mirror does not suffer from the finite Beta

2 Ability to operate close to the power supply is an important issue on IC design

3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L

4 - VA lower for MOS

IREF

IO

IE

IO

IREF

IREF

I

E

1 2

2

1

1

1

2

R

ro

2

A factor greater the then simple

Current source

Disadvantage: reduced output swing.

Observe that the voltage at the collector at

Q3 has to be greater than the negative

supply voltage by

(vBB1 = VCEsat-3), which is about a volt.

Exercise 6.10

2

1

2

1 2

2

1

2 I E

IREF

I E

IO

I E

IE

I E

I E

I E

1

IE

IE

IE

IO

IREF

IO

IREF

1 2

I

E

2

1

2

IE

2 2

important way: a resistor RE is included in

the emitter lead of Q2. Neglecting the base

current we can write:

VB1

IREF

VT ln

VB1 VB2

VB1

IO RE

IS

VB2

IREF

VT ln

IO

VB2 IO RE

IREF

VT ln

IO

IO

VT ln

IS

Example 6.2

Example 6.3

Example 6.3

Calculating 1st stage gain

-- Assuming

V

100

re1 re 2 I TE .25

25

Model Eqs. on Pg. 263

re

gm

( VI ) ( I

VT

( 1 )

r 1 r 2 ( 1)(re )

101*100 10.1k

Rid r 1 r 2 20.2k

In the same manor

Ri 2 r 4 r 5

Ri 2 2 ( 1) r

2 (101 25) 5.05k

Total collector resistance

1

Ri2

A1

vo 1

vid

I C RC _ Total _ R

I E RE _ Total _ R

Ri 2 ||( R1 R2 )

re1 re 2

5.05 k||40 k

200

22.4 VV

Calculating 2nd stage gain

Ri3

Ri 3 ( 1)( R4 re 7 )

re 7

VT

IC

25

1

25

234.8k

re4 and re5 calc. before

A2

R3 || Ri 3

re 4 re 5

3 k||234.8 k

50

59.2

V

V

Calculating 3rd stage gain

Purpose is to allow amplified

signal to swing negatively

re8

Ri4

25

5

Ri 4 ( 1)(re8 R6 )

101(5 3000) 303.5k

A3

vo 3

vo 2

R5 || Ri 4

re 7 R4

15.7 k||303.5 k

2.325 k

6.24

V

V

Calculating 3rd stage gain

vo

vo 3

A4

3000

3005

R6

re 8 R6

.998 VV

Overall Gain

A

Output Resistance

vo

vid

A1 A2 A3 A4 8513 VV

Ro R6 || (re8

R5

1

) 152

vo

g m v d Ro

ro2 ro4

Ro

ro2

ro2 ro4

ro

Ro

vo

vo

g m ro

vd

IC

gm

ro

VT

g m ro

VA

VT

ro4

2 r

ro

g m v d

VA

IC

IC

I

2

Ri

ro

Gm

gm

VT

MOSFET Operation

Problem 6.1

RC 3000

at

vBE 0.7

iC 0.0005

vE vCM vBE

iC1

iC

iC 0.001

vCM 2

vE 2.683

4

iC1 4.95 10

vC1 3.515

0.5

1

VCC 5

vBE 0.683

100

Problem 6.15

vd 0.1

ie

re 25

vd

2 ( re RE)

RE 100

4

iE1 1.4 10

iE2 IE ie

iE2 6 10

vc1 ie RC

vc1 2

vc2 vc1

vd

RC 5000

ie 4 10

iE1 IE ie

Ad

IE 0.001

Ad 40

vc2 ie RC

vc2 2

Purpose

The purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuits behavior needs to be

modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and

simulated results is required for the relative validity of the models.

This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.

Procedure

Construct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power

Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).

Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current

and collector current. From these current values calculate .

Figure 2

circuit shown in Figure 2.

All transistors are

MPQ2222 Bipolar Junction

Transistors. Use PSpice to

construct the circuit.

Measure the DC values at the

collector of Q1 and Q2. Do

the measured values agree

with theoretical ones.

Measure the DC value at the

emitter of Q1 and Q2. Do

the measured value agree

with the theoretical one.

Indicate the inverting and noninverting output.

Input an AC signal into Q1 of

your circuit at frequencies .

What is the single voltage

gain of your circuit?

Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC

operating point of the amplifier. Bias point voltages are measured and then compared to

the bias points produced by the PSpice simulation. Record DC bias point data.

Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031

V and apply to one of the input terminals and the other terminal remained grounded, as

shown in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A MultiMeter the output of the amplifier to observe input signal frequencies. Determine the corner

frequency (3-dB point) of the output and compared with the corner frequency generated

with an AC sweep in PSpice. Plot the PSpice AC sweep simulation.

Next calculate the differential mode voltage gain, AV-dm, from the laboratory data and

compare to the AV-dm predicted by the PSpice simulation and theoretical equations. Both

inputs are tied together to create a common mode signal on the input terminals. The

output voltage is then used to calculate the common mode voltage gain, A V-cm, and then

compared to the AV-cm predicted by the PSpice simulation and theoretical equations. From

these values the common mode rejection ratio (CMRR) should be calculated for each

case.

Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The

resistors were all given standard unbridged values and were allowed to vary uniformly

within 5% of the nominal resistor value. The transistors should be given a nominal value

(say 175) and allowed to vary uniformly to +/- 100. The variations of differential and

common mode gains should be graphed on two histograms.

Analysis / Questions

What are the values of for the first transistor?

(typical values of range from approximately 125 to 225)

With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the

PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there

would be little change in values from one transistor to the next, making the previous assumption

reasonably valid.

How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation?

What is the reason for the small differences between measured and predicted voltages?

Exercises 6.17

Exercise 6.19

BiCMOS Amplifiers

Exercise 6.20

BiCMOS Amplifiers

Exercise 6.21

BiCMOS Amplifiers

Exercise 6.22

Current sources Exercise 6.23

A Cascode Current Source Exercise 6.24

Increasing The Output Resistance by Bootstrapping

A Simple Cascode Configuration The Composite Transistor

Differential Amplifiers

Multistage Amplifiers

Example 6.4

Multistage Amplifiers

Example 6.5 SPICE Simulation of a Multistage Amplifier

- chapter 3.pptxUploaded byARif Hakim
- Stereo Amplifier Assembly ManualUploaded byAndrés Polochè Arango
- ECX 4150 Assignment 1 - 2016Uploaded byUditha Muthumala
- LIC-II-ECE-NOTESUploaded bySunil Gavaskar
- B-stad_CH_05.pdfUploaded byOzan Dokuyucu
- 1Uploaded byHamza Ali
- Cs amplifierUploaded byHarsha
- Report 1 Electro2Uploaded byersgd
- Chapter 5 - ele232_feb11 [Compatibility Mode] (1).pdfUploaded bykavish malaka
- ELECS-LAB-1Uploaded byKiel Dalisay
- Electronic Circuits - I Lecture Notes for B.E. (ECE) (Low Resolution)Uploaded bycmkmangai
- Electronics Lab 15Uploaded byahkiaenaaaa
- Chen - VLSI Handbook [CRC Press 1999]-CHP20Uploaded byfeki2607
- Eeeb273 1011s1 Mt QnaUploaded byMohd Rashdan
- DCIO PaperUploaded byAnil Verma
- DC Baising and Operation of JFET AmplifierUploaded byHilda Sikwa'ae
- 2-A Novel Circuit ModelUploaded byhakik
- bsnl mixed sample papersMixed 2Uploaded byPravin Kumar Gupta
- lect07Uploaded byAtharvaSarage
- Audio Amp DNAUploaded byTiras Ngugi
- MC33191 - Automotive 12V Ignition DriverUploaded bycronoss21
- J-601-1448_lec04.pdfUploaded byAnkit Prajapati
- EC I-lab manualUploaded bychenthiltr
- 4 - 5 - Ideal and Real Current Sources (7_43)Uploaded byEdyar Rafael
- ECA Course Description, NEWUploaded bymalladhinagarjuna
- Bhel PaperUploaded byAnkit Srivastava
- B.Tech-ECEUploaded byAnand J
- VIPer20A DatasheetUploaded byikaro181083
- Analogue II Lab2Uploaded byCrispin Hung
- AEC Exercise5Uploaded byMananga destaing

- qfticUploaded byvidhya.dpi5566
- Unfeeling DeficientUploaded byalinvfx
- Introduction to VLSI SystemUploaded byyugant7
- Vlsi Write Up-2016 17 GbUploaded bySaurabhMoharir
- Power Comparison of CMOS and Adiabatic Full Adder CircuitsUploaded byAnonymous e4UpOQEP
- MBISRUploaded byjai_vardhan789
- Naveen Ppt 3d ic technologyUploaded byG NAVEEN KUMAR
- Smd TutorialUploaded byAnkur Shukla
- FET Basics 1Uploaded byGene Palencia
- Ece532 Pres Ekv BsimUploaded byKenneth Palma Carmona
- IRF530Uploaded byRuben Sosa Monroy
- Fermi FET TechnologyUploaded bynvbond
- IGBT MitsubishiUploaded bymadhuvariar
- Diode Cross ReferenceUploaded bytaz313
- 2SD 717 _ISCUploaded byUnfinished_projects
- Effect of O2 Annealing in N-contactUploaded bypawanceeri1965
- Mosfet 01Uploaded byEdward Allan Mangubat
- Transistor Tutorial About Bipolar and FET Transistors-nupUploaded bylosmilzo
- Basic Electronics Lecture Notes.pdfUploaded byMd.Arifur Rahman
- Mje 13001Uploaded byNicoleta Gherman
- 6N60Uploaded byDan Roads
- FinFETs ‐ Technology and Circuit Design ChallengesUploaded byHarrison Malagon
- WPE-20-1Uploaded byvuaphu
- Component Replacements for My Electronics ProjectsUploaded byJohn Vince Ramos Pap
- C5305Uploaded byMarcio Dias
- Electronic Devices Model Question PapersUploaded byk_kunaraj
- dept_34_lv_3_17592Uploaded byDiogo Gonçalves Oliveira
- SSE 2010-SOI Versus Bulk-silicon Nanoscale FinFETsUploaded byWenqi Zhang
- Logic GatesUploaded byMahavira Desai
- CSE-III-ELECTRONIC-CIRCUITS-10CS32-NOTES.pdfUploaded bykingraaja