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I7s Core

Jon Ross
&
Philip Cosgrave

Intels Core i7
Jon Ross
&
Philip Cosgrave

Content

Overview
Socket
SSE 4.2 Instruction Set
Cores
Intel Quickpath Interconnect
Nehalem - new micro-architecture
EP, EX socket
3 to 2 chip solution

Over View

Released November 2008


CPU clock
Cache
Turbo Boost

Socket
Known as the LGA 1366 or Socket B
Contact points

Instruction Set
Backwards support
Added SSE 4.2 Instruction set

CRC32
PCMPESTRI
PCMPESTRM
PCMPISTRI
PCMPISTRM
PCMPGTQ
POPCNT

Core: Over View


4 Physical, 8 logical from H/T
3 channel memory

Core: Intel Quickpath Interconnect

Intel X58 Arch


Replaced front side bus
Max width: 20 bit
Max bandwidth: 16GB/s Unidirectional
I7 920, 940
16 bit and 4.8 GT/s = 19.2 GB/s

I7 965XE
16 bit and 6.4 GT/s = 25.6GB/s

Core: Nehalem
45nm architecture
Scalable performance for from one-to-16 (or
more) threads and from one-to-eight (or
more) cores.
Power usage

Core: EP & EX
EP is for 2 sockets (the base layout)
EX is for 4 and 8 sockets
Is the EP duplicated with more interconnects

Core: 3 to 2 chip solution


Named Westmere
Moved GPU functionality from the
Northbridge onto the CPU
Enables full disk encryption

Other Fun Info

More Extra Info

References

Crysis Benchmark:
http://www.pcgameshardware.com/aid,665558/Intel-Core-i7-Nehalem-CPUs-reviewed/Reviews/?
page=5
Pin set:
Intel Core i7 Extreme Edition and Intel Core i7 Processor and LGA1366 Socket
http://download.intel.com/design/processor/designex/320837.pdf
Intel Overclock:
http://www.engadget.com/2008/12/03/intels-core-i7-extreme-edition-965-overclocked-to-5-5ghz/
Intel Nehalem Arch
http://download.intel.com/pressroom/kits/events/idffall_2008/SSmith_briefing_roadmap.pdf
2 vs 3 chip solution
http://www.neoseeker.com/Articles/Hardware/Reviews/intel_32nm/4.html
Intel i7 homepage
http://www.intel.com/products/processor/corei7/index.htm
Intel Quickpath
http://www.intel.com/technology/quickpath/introduction.pdf
Intel Turboboost
http://www.intel.com/technology/turboboost/index.htm
Nehalem Arch
http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf

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