FETs 2 (MOSFETs)

Lecture 3
31/10/2005

Anthony Herbland

Course Content
Op-amps
FETs
Oscillators
A/D

& D/A converters

Lecture Content
Revision

of p-n junction diodes

The FET family
The JFET (n-channel)
JFET Models and Biasing
MOSFET / IGFET

Depletion type
Enhancement type
Switch mode

Sample

& Hold Circuit

3

Relationships
JFET

BJT

VGS
I D I DSS 1
VP

ID IS

IG 0 A

IC I B

IC ; I E

VBE ; 0.7V

C
ID

IG=0A

VGS

IC

V
I D I DSS 1 GS
VP

IS

VBE 0.7V

IB

IC I B
IE

E
4

Comparison between JFETs &

MOSFETs
Both

have Drain, Gate and Source

Both are controlled by a gate-to-source
voltage
Difference:

MOSFET has its Gate terminal isolated

Insulated Gate FET (IGFET)
MOSFET is broken into 2 types:

Depletion type
Enhancement type
5

Symbols
Depletion

type (n-channel)

Depletion

type (p-channel)

Enhancement

type (n-channel)

Enhancement

type (p-channel)
6

n-channel depletion-type
MOSFET: Construction
SiO2

Drain (D)

n-channel

n+

Metal
contacts

Gate (G)

p
Substrate

Substrate
SS

n+

Source (S)

n-doped
regions

n-channel depletion-type
MOSFET: Description
Source

(S) and drain (D) terminals connected

to n-doped regions linked to the n-channel.

p-type

material (substrate) is sometimes

connected internally to the source terminal.

Gate

terminal connected to metal contact but

insulated by a thin silicon dioxide layer (SiO2).

So

no connection between the gate terminal

and the channel of a MOSFET.
8

n-channel depletion-type
MOSFET: Basic Operation

n+

G
n

VGS = 0V

SS

VDD
-

n+

ID = IS = IDSS
9

n-channel depletion-type
MOSFET: Vgs=0V
With

Vgs = 0 and Vds positive

Increasing Vds will eventually result in pinch-off, as for

JFETs.

IIDD
IDSS

Saturation level (VGS = 0V)

n-channel resistance (rDS)

D
G

VGS = 0V

SS

VDD
-

0
0

VP

V
VDS
DS

ID = IDSS

10

n-channel Depletion-type
MOSFET: Characteristic
Depletion
mode

ID

Enhancement
mode
VGS = +1V

IDSS

VGS = 0V
VGS = -1V
VGS = -2V
VGS = -3V

VGS

-4

VGSoff
VP

-3

-2

-1

VGS = -4V
|VP|

VDS
11

n-channel Depletion-type
MOSFET
With

Vgs < 0, and Vds constant positive

The ve potential at the gate tends to pressure

the electrons toward the p-channel substrate.

Also attracts the holes from the p-channel

substrate.

The conduction then reduces

Therefore the device is in depletion mode.

12

n-channel Depletion-type
MOSFET
With

Vgs > 0, and Vds constant positive

The electric field across the insulating layer will

attract electrons out of the channel.

Conduction (Id) will then increase.

The positive VGS enhances the level of free

carriers in the channel.

Therefore the device is in enhancement mode.

13

p-channel Depletion-type
MOSFET: Description
Its

construction is exactly the

reverse of the n-channel
depletion MOSFET

Drain (D)
p+

Gate (G)

All

the voltage polarities and

the current directions are
reversed

Substrate
SS
n
Substrate

p+

Source (S)

14

p-channel Depletion-type
MOSFET: Characteristic
ID

ID
IDSS

VGS = -1V

VGS = 0V
VGS = +1V
VGS = +2V
VGS = +3V

-1

4 VGS
VP

VGS = +4V
VDS
15

n-channel Enhancement-type
MOSFET: Description
There

is no n-type channel
Drain (D)
between the drain and the
source.
n
p substrate is extended to
p
Substrate
Gate (G)
the SiO2 layer
+

Substrate
(SS)

n+

Source (S)

16

n-channel Enhancement-type
MOSFET: Description
A

positive gate voltage (VGS > 0) attracts

electrons from the substrate to the region
along the insulating layer opposite the gate.
With enough electrons, that region is
converted to N-type channel.
Therefore, making VGS more positive
enhances the conductivity of the channel.

17

n-channel Enhancement-type
MOSFET: Characteristic
ID

ID

VGS = 8V

VGS = 6V
VGS = 4V
0

2
VP
VT

8 VGS

VGS = 2V
VDS
18

n-channel Depletion MOSFET

Drain

Id
Vds

Gate
Vgs

Source

19

n-Channel Depletion MOSFET:

ID vs VGS
Vds = 3V
600.00u

Id [A]

400.00u

I D

200.00u

VGS

I D
gm
VGS

0.00
-2.00

-1.00

0.00

1.00
2.00
Vgs [V]

3.00

4.00

5.00

20

n-channel Depletion MOSFET:

ID vs VDS
Vgs = 0 V

500.00u

Id [A]

400.00u

Vgs = 2 V

300.00u
200.00u

Vgs = 4 V
100.00u
0.00
0.00

1.00

2.00

3.00
Vds [V]

4.00

5.00

21

Depletion-type Model
The

transfer characteristic extends into the

enhancement mode and then appears to be
quite linear.
This example has a gm of only about 90S in
the linear region.
The output characteristics are linear above
pinch-off.
This example exhibits quite a low RDS of
about 40k above pinch-off.
22

n-channel Enhancement
MOSFET
Type 2N6755

Drain

VP= 3.13V

Id
Vds

Gate
Vgs

Source

23

n-channel Enhancement
MOSFET
Type: 2N6755 Vp = 3.17 V
3.00

Id [A]

2.00

1.00

0.00
3.00

3.25

3.50
Vgs [V]

3.75

4.00

24

n-channel Enhancement
MOSFET

Current [A]

900.00m

Vgs = 3.6 V

Vgs = 3.5 V

600.00m

Vgs = 3.4 V

300.00m

Vgs = 3.3 V
Vgs = 3.2 V

0.00
0.00

1.00

2.00
Input voltage [V]

3.00
25

Enhancement-Type Model

The transfer characteristic is fairly linear at high Vds,

but look at the current.
This would mean un-acceptably low values for Rd
and Rs, and very high power dissipation. This device
needs to be operated close to its threshold.
This example has a gm of about 2.8S at Vgs = 3.6V,
and 1.2S at Vgs = 3.25V.
The output characteristics are virtually horizontal
above pinch-off.
This example exhibits an rds of about 1.4G.
26

Biasing & Characteristics

The

models and bias designs are the same

as for the JFET
R2

Rd
C2

15V

Vout
C1

Vin

R1

Rs

Ce

Rld

Rf

27

Small-Signal MOSFET Model

with Feedback
g
vgs
vin

R1

d
gm .vgs
rds

R2

Rd

Rl

vout

Rf

28

MOSFET Model with Feedback

vin vgs g m v gs R f
vout g m vgs R x

Vout
gmR x
Av

Vin
1 gmR f

where R x rds //R d //R l

Rx
1

Rf

if

g m R f 1

29

MOSFETs as switch
Most

semiconductor devices are basically

switches.
Thus a p-n junction device effectively turns
on and off when its threshold voltage is
exceeded or not.
FETs are no different in this respect, but have
the added advantage of very high input
resistance.
This significantly reduces input currents when
used as logic gates.
30

MOSFETs as switch (Contd)

5V

dig

fet

out

31

MOSFETs as switch (Contd)

A pulse generator is driving the FET with a pull-up

resistor to 5V. Even though logic high at the input is
3.4V, the FET is switching between 0V and 5V. The
inverting buffer restores the logic pulses if required.

A very useful application of this type of circuit is in

the restoration of logic levels to +5V and 0V, for use
in ADC and DAC circuits, for example. This also
introduces the concept of Complementary Metal
Oxide Semiconductor devices (CMOS).
32

MOSFETs as switch (Contd)

dig

4.00

fet

0.00
5.00

out

0.00
4.00

0.00
0.00

2.50m

5.00m
Time [s]

7.50m

10.00m

33

CMOS

Consists of p channel & n

channel MOSFETS incorporated
in the same package.
The circuit below is a basic
CMOS inverter. The PMOS (Q2)
has a threshold of 3.36V; the
NMOS (Q1) has +3.13V.

5V

Vg
VGS-Q2

PMOS Q2

Vout
NMOS Q1

VGS-Q1

The source of Q2 is connected to

+5V, the source of Q1 to ground.
34

CMOS (Contd)
With

logic high (say 3.4V) at the common

gates Q2 will be turned off because Vgs will
be 3.45 = 1.5 (< 3.36V). But Q1 will be
turned on and the output will be pulled to
ground (0V).

With

logic low (say 0.25V) at the gates, Q1 will

be turned off. But Q2 will be turned on
because Vgs will be 0.255 = 4.75 (>
3.36V), and the output will be pulled to +5V.
35

CMOS (Contd)
This

circuit can be used as a "logic restorer",

as shown in the circuit below. This is
sometimes known as an input data latch.
Vin

Vg

5V

PMOS

Vout
Digital input

NMOS

36

CMOS (Contd)
The

digital input is inverted and then applied

to the CMOS inverter. Whatever the logic low
or high levels are at the input, the output will
be 0V or +5V. Very useful for feeding digital
to analogue converters (DACs).

37

CMOS (Contd)
Vg

4.00

Vin

0.00
3.00

Vout

0.00
5.00

0.00
0.00

2.50m

5.00m
Time [s]

7.50m

10.00m

38

Lecture Content
Revision

of p-n junction diodes

The FET family
The JFET (n-channel)
JFET Models and Biasing
MOSFET / IGFET

Depletion type
Enhancement type
Switch mode

Sample

& Hold Circuit

39

Sample and Hold Circuit

This

is another useful application of

MOSFETs as switches, and also finding an
application in the digital-analogue interface
e.g. analogue to digital converters (ADCs).

40

Sample and Hold Circuit (Contd)

Sample & Hold Circuit
Voltage-controlled
FET switch

FET input op-amp.

17

Rin = 2

1Vpk 50 Hz

Level shift

ohm

IRF121

VP1

Vout

TL071C

VP2

VP3
100nF

41

2.50
2.00

1.00
0.50

VOUT

0.00
-0.50

VC

-1.00

VIN

-1.50
20.00m

30.00m
Time (s)

5.00

40.00m

VP3

Output

1.50

-1.00
24.00m

25.00m

26.00m
Time (s)

27.00m

42

Sample and Hold Circuit (Contd)

The

FET is turned on & off from a gate drive

source at a sampling rate that needs to be
high to avoid distortion.

In

the example, the sampling rate is low

(10:1) in order to clarify the operation of the
circuit. The on time of the FET in this
example is only 10s every 2ms (one tenth of
the period of the signal, which is 50 Hz).
43

Sample and Hold Circuit (Contd)

The

capacitor will be charged to the voltage

level of the signal at the sampling point.

The

capacitor will not discharge due to the

very high input resistance of the op-amp
buffer i.e. the output will "hold" at the sampled
level.

44

Sample and Hold Circuit (Contd)

This

circuit also includes a very crude "level

shifter" to ensure the samples are positive for
future manipulation by an ADC for example.

Despite

the very low sampling rate used here,

the total harmonic distortion (THD) of the
output is surprisingly only 17%. Quadrupling
the sampling rate reduces this to 3.5% etc.
45

References

T.F. Bogart, Linear Electronics, Macmillan Publishing

Compagy, 1994.

R.L. Boylestad & L. Nashelsky, Electronic Devices and Circuit

Theory, Pearson Education, 2005.

46