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3D FinFET using 14 nm technology

node:

IC fabrication
advancements

The SOI MOSFET:from single gate to


multigate

The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor


is a semiconductor device which is widely used for switching and
amplifying electronic signals in the electronic devices. The MOSFET is a
core of integrated circuit and it can be designed and fabricated in a single
chip because of these very small sizes. The MOSFET is a four terminal
device with source(S), gate (G), drain (D) and body (B) terminals. The body
of the MOSFET is frequently connected to the source terminal so making it
a three terminal device like field effect transistor.

Working of a mosfet

When V GS<V T(depletion), there is a deficit of electrons and


holes making the channel very highly resistive.hence no drain
current can flow

When VDS>0, AND VGS> VT, the induced n type region allows the
current between the source and the drain.

Working of a mosfet
As we keep on increasing Vds,the
depeltion region near the drain
widens hence decreasing the
electron concentration and hence the
channel conductance is reduced.
Further increasing the vds, the
inversion layer eventually disappears
creating a condition of pinch-off.

Mosfet scaling
Keeping in pace with the Moores law and ITRS roadmap mosfet
scaling ,i.e, reduction in the overall size of the mosfet , helps
increase the speed, and lowering of the harmonic distortion. But
as the channel length approach and fall below 100 nm,New
characteristics are observed many of them are undesirable.
As the dimensions of the transistors are shrunk, the close
proximity between the source and drain reduces the ability of the
gate electrode to control the potential distribution and the flow of
current in the channel region, and undesirable effects,called
short-channel effects starts plaguing MOSFETs.
Short channel effects arise when the control of the channel region
by the gate is affected by electric field lines from source to drain.

Gate geometry and electrostatic integrity

Short channel effects arise when the control of the channel region by the
gate is affected by electric field lines from source to drain

Finding the solution:double gate


structure
A much more efficient device
configuration is obtained by using
the double gate transistor
structure.This device structure was
first proposed by Sekigawa and
Hayashi in 1984 and was shown to
reduce threshold voltage roll off in
short channel devices.

Finding the solution:double gate


structure

An important conclusion can be derived from the data presented in


figure:bulk transistors run out of steam once they reach a gate
length of 15-20 nm.FDSOI can be used until 10nm, but smaller gate
lengths can be only achieved by the double gate structure.

Mosfet contrast from single gate to


multiple gates

In a continuous effort to increase current drive and better control


short channel effects, SOI MOS transistors have evolved from
classical,planar,single gate devices into three dimensional
devices with multi gate structure

Muti fin multi gate mosfet

Multi gate finfet process


flow

Fin patterning(1.) 193 or 193i lithography


(2).extreme ultraviolet lithography
Alternative fin fabrication technique-spacer definer patterning technique

Fabrication sequence of a multi gate


mosfet

Gate patterning
considerations

Scaling Reduce power: The tunnelFET (tFET)

Stand-by power dissipation


approaching on power dissipation
Cannot continue like this!
60 mV/dec VG 250 mV for Iof/Ion
10-4
VT + VG 0.45 V at 300 K (nFETs)
Must increase slope (i.e., go below
60 mV/dec) if we want the `Green FET
(term coined by C. Hu)
Problem: Ion too low in all attempts
(DARPA to IBM, UCB, Stanford,) so far

Scaling Reduce leakage


Off-leakage:
Accepted value increasing: Iof/Ion 10-4 for the 32 nm node (used to
be 10-6 or lower!)
Connected to electrostatic integrity (punch-through, junction
leakage, gate leakage)
Gate leakage:
C = ox/tox, so if tox has reached its limit ( 1nm, too aggressive so
far), scale ox:
High- insulators such as HfO2,
ZrO2, Al2O3, etc.
Problem: Low mobility in high- MOS systems (scattering with
interfacial optical phonons)
Metals with different workfunction needed!

Hi-res TEM from


Susanne Stemmer,
UCSB

Scaling Reduce leakage: Gate oxide scaling at Intel

Scaling Improve performance

Application of finfet:SRAM

Application of finfet:silicon nanowire


transistors

Silicon nano wire transistors may be a candidate for sub 10nm technology nod

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