Professional Documents
Culture Documents
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BITS Pilani Dr. Virendra Singh Shekhawat
Department of Computer Science and Information Systems
Pilani Campus
Topics
Address
Control
Processor
Data bus Main
Registers Memor
y
Address
Control
Data bus
Computing
Apps such as web servers, video
conferencing, database server, streaming
etc.
Networking
Provides connectivity between computing
nodes
e.g. web service running on a computing
node talks to a database service running
on another computer
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Storage (Persistent + Non-Persistent)
BITS Pilani, Pilani Campus
Memory Requirements
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BITS Pilani, Pilani Campus
Memory Bandwidth
Requirement[2]
DEC VAX Early Superscala Hyperthre
11/780 pipelines rs aded
(circa 80) (circa 90) (circa 00) Multi-cores
(circa 08)
Clock Cycle 250ns 25ns 1ns 0.4ns
Instructions 0.1 1 2 (4-way) 8 (quad
per cycle core,2
threads/core
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BITS Pilani, Pilani Campus
Memory Bandwidth
Requirement[3]
DEC VAX Early Superscala Hyperthre
11/780 pipelines rs aded
(circa 80) (circa 90) (circa 00) Multi-cores
(circa 08)
Clock Cycle 250ns 25ns 1ns 0.4ns
Instructions 0.1 1 2 (4-way) 8 (quad
per cycle core,2
threads/core
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BITS Pilani, Pilani Campus
Memory Bandwidth
Requirement[4]
DEC VAX Early Superscala Hyperthre
11/780 pipelines rs aded
(circa 80) (circa 90) (circa 00) Multi-cores
(circa 08)
Instructions 4 * 105 40 * 106 2 * 109 20 * 1010
per second
Instruction 3.8B 4B 4B 4B
Size
Operands in 1.8 *4B 0.3 *4B 0.25*4B 0.25*4B
memory per
instruction
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BITS Pilani, Pilani Campus
Memory Bandwidth
Requirement[5]
DEC VAX Early Superscala Hyperthre
11/780 pipelines rs aded
(circa 80) (circa 90) (circa 00) Multi-cores
(circa 08)
Instructions 4 * 105 40 * 106 2 * 109 20 * 1010
per second
Instruction 3.8B 4B 4B 4B
Size
Operands in 1.8 *4B 0.3 *4B 0.25*4B 0.25*4B
memory per
instruction
BW Demand = Instructions per second * (Instruction size +
Operand size)
BW Demand 4.4 Mbps 208 Mbps 10 Gbps 100 Gbps
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BITS Pilani, Pilani Campus
Memory Hierarchy[1]
Locality of reference
Memory references are clustered to either a
small region of memory locations or same set
of data accessed frequently
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BITS Pilani, Pilani Campus
Memory Hierarchy[2]
How do we meet memory bandwidth
requirements?
Multiple levels
Early days register set, primary, secondary and
archival
Present day- register set, L1 cache, L2 cache,
DRAM, direct attached storage, networked storage
and archival storage
Motivation
Amortization of cost
As we move down the hierarchy cost decreases and
speed decreases.
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BITS Pilani, Pilani Campus
Memory Hierarchy[3]
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BITS Pilani, Pilani Campus
Memory Hierarchy:
Performance
Exercise:
Effective Access time for 2-level hierarchy
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BITS Pilani, Pilani Campus
Memory Hierarchy:
Memory Efficiency
Memory Efficiency
M.E. = 100 * (Th/Teff)
M.E. = 100/(1+Pmiss (R-1)) [R = Th+1/Th]
Maximum memory efficiency
R = 1 or Pmiss = 0
Consider
R = 10 (CPU/SRAM)
R = 50 (CPU/DRAM)
R = 100 (CPU/Disk)
What will be the Pmiss for ME = 95% for each of
these?
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BITS Pilani, Pilani Campus
Memory Technologies-
Computational
Cache between CPU registers and main
memory
Static RAM (6 transistors per cell)
Typical Access Time ~10ns
Main Memory
Dynamic RAM (1 transistor + 1 capacitor)
Capacitive leakage results in loss of data
Needs to be refreshed periodically hence the term
dynamic
Typical Access Time ~50ns
Typical Refresh Cycle ~100ms.
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BITS Pilani, Pilani Campus
Memory Technologies-
Persistent
Hard Disks
Used for persistent online storage
Typical access time: 10 to 15ms
Semi-random or semi-sequential access:
Access in blocks typically of 512 bytes.
Cost per GB Approx. Rs 5.50
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BITS Pilani, Pilani Campus
Caching
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BITS Pilani, Pilani Campus