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CMOS VLSI
Design
Si Si Si
Si Si Si
Si Si Si
Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si
Si Si Si Si Si Si
p-type n-type
anode cathode
p bulk Si
0
n+ n+
S D
p bulk Si
1
n+ n+
S D
p bulk Si
p+ p+
n bulk Si
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
A Y VDD
0
1
A Y
A Y
GND
CMOS VLSI Design
Fabrication andSlide
Layout
12
CMOS Inverter
A Y VDD
0
1 0 OFF
A=1 Y=0
ON
A Y
GND
CMOS VLSI Design
Fabrication andSlide
Layout
13
CMOS Inverter
A Y VDD
0 1
1 0 ON
A=0 Y=1
OFF
A Y
GND
CMOS VLSI Design
Fabrication andSlide
Layout
14
CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B
Y
A
B
C
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
p+ n+ n+ p+ p+ n+
n well
p substrate
GND VDD
n-well
Polysilicon
Polysilicon
n+ diffusion
p+ diffusion n+ Diffusion
Contact p+ Diffusion
Metal Contact
Metal
p substrate
SiO2
p substrate
Photoresist
SiO2
p substrate
Photoresist
SiO2
p substrate
Photoresist
SiO2
p substrate
SiO2
p substrate
n well
n well
p substrate
Polysilicon
Thin gate oxide
n well
p substrate
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
n well
p substrate
n+ Diffusion
n well
p substrate
n+ n+ n+
n well
p substrate
n+ n+ n+
n well
p substrate
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
Contact
n well
p substrate
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate