Professional Documents
Culture Documents
2
VGS
ID = IDSS 1 -
VP
VGS = - VGG
2
VGS
ID = IDSS 1 -
VP
Since VGS = - VGG
2
VGG
ID = IDSS 1 -
V P
2
VGS
ID = IDSS 1 -
VP
2
VGG
ID = IDSS 1 -
VP
IG = 0
VRG = 0
Input Output
R2 -VG + VGS + IDRS = 0 VDS = VDD - ID (RD + RS)
VG = VDD
R1 + R2 VGS = VG - IDRS
January 2004 ENGI 242/ELEC 222 18
JFET Voltage Divider Bias Load Line
With an N Channel
D-MOSFET,
VGS may be positive
IG = 0
VGS = VDS
VGSTH = 4V
VGSon = 7.5V
IDon = 5mA
VDD = 22V
IDon
k=
(VGSon - VGSTH)2
ID = k(VGS - VGSTH)2