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LECTURE
Andrew Brown
Jonathan Warner
Laura Strickland
Table of Contents
Signals
Applications of ADCs
Types of ADCs
Successive Approximation Example
The ADC on the MC9S12C32
Introduction
Analog to digital converters convert analog, or real world
signals to a series of 1s and 0s, able to be stored or
transmitted through computers or digital systems.
Introduction cont.
Reasons why this would be needed:
Digital storage of a non-digital signal
(ex: recording light intensity of a lightning strike using sensors, mapping
a flight path of an aircraft onto a computer for analysis)
Transmitting data over a digital system
(ex: sending your voice through a telephone system, Skype chatting,
etc)
Analog Signals
Analog signals are the smooth, real, signals of the world.
Assigning a binary
code value to discrete
measurements, stored
on a fixed-length
variable.
Quantization Noise
Since values are rounded to the nearest possible digital
value, a certain level of quantization noise will occur.
Example: In an 8-bit resolution system, a value of 236.4
will be stored as the digital value 236.
2^n-1 comparators
Parallel Design (Flash ADC)
Advantages Disadvantages
Fastest ADC 2^n-1 comparers
(gigahertz) Low resolution
Simple Design Large Die size
Can achieve Prone to glitches
non-linear output (out of sequence
output)
Successive Approximation
DAC-Based Design
Advantages Disadvantages
Speed, worst case
Resolution tradeoff
n clock cycles with speed
Conversion time
independent of
amplitude of Vin
Capable of outputting
the binary number in
serial (one bit at a time)
format.
Dual-Slope
Integrator-Based Design
Switch connects Vin with
integrator
Switch held for fixed
number of clock cycles
Analog switched at set time
to Vref
T2 clock cycles
proportional to Vin
Vin = Vref x T2/T1
Dual-Slope
Integrator-Based Design
Dual-Slope
Integrator-Based Design
Advantages Disadvantages
Insensitive to Speed, 2^n-1 clock
components value cycles
errors
Limited applications
Can achieve high
resolution (but at the
cost of speed)
Useful for highly
accurate
measurements
Sigma-Delta
Analog signal set to
integrator
Resulting sawtooth
waveform compared with
zero volts
Output either high or low
Clock rate used is very high,
Output converted to positive or results in oversampling of data
negative Vres and fed back to be
added to next samples Vin
Resulting stream of 0s and 1s
represents the analog signal
average voltage
Sigma-Delta
Advantages Disadvantages
High Resolution Speed,
No need for precision Oversampling
components Only applicable for
low bandwidth
ADC Comparison
0 0 1 1 1 0 0 0 0.4 <0.4375
0 0 1 1 0 1 0 0 0.4 <0.4063
0 0 1 1 0 0 1 1 Digital
Output
The ATD10B8C on the MC9S12C32
Input Pins
ATD10B8C
MC9S12C32 Block Diagram
The Basics of the ATD10B8C
Resolution: 8- or 10-bit (manually chosen)
8-channel multiplexed inputs
Successive Approximation architecture
Can perform single or continuous sampling
Can sample single or multiple channels
Conversion time: 7 s (in 10-bit mode)
Optional external trigger
ATD10B8C Block Diagram
Pin Purposes
AN7/ Analog input channel
ETRIG/ 7/
PAD7 External trigger for
ADC/
General purpose
digital I/O
AN6/PAD6 Analog input/
AN0/PAD0 General purpose
digital I/O
VRH, VRL High, low reference
voltages
VDDA, VSSA Supply power for analog
circuitry
Control Register 2
Pin Description
Pin Description
6-3 Controls the number of conversions per sequence
2 0 ATD Conversion calculation goes to
corresponding result register
1 Current ATD conversion put in consecutive result
registers; wraps around sequentially at end
1-0 Determines how ATD responds to a breakpoint (see
Table 8.5)
Control Register 4
Pin Description
7 0 10-bit resolution
1 8-bit resolution
6-5 Selects the length of the second phase of the
sample time in units of ATD conversion clock
cycles. (See Table 8-7)
4-0 ATD Clock Prescaler (PRS) (5 bits long). ATD
conversion clock frequency is calculated by:
BusClock
ATDclock = * 0.5
PRS +1
Control Register 5
Pin Description
7 0 Data in the result registers is left-justified
1 Data in the result registers is right-justified
6 0 Result register data is unsigned
1 Result register data is signed
5 Continuous Conversion Sequence Mode
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
4 Multi-Channel Sample Mode
0 Sample only one channel
1 Sample across multiple channels
2-1 Selects the analog input channel(s) whose signals are
sampled and converted to digital codes (See Table 8-12)
Single Channel (MULT = 0)
Single Conversion (SCAN = 0)
ATDDR7
ATDDR6
7 6 5 4 3 2 1 0 ATDDR5
ATDDR4
ATDDR3
Port AD
Result ATDDR2
Register
Interface ATDDR1
ATD Converter ATDDR0
Single Channel (MULT = 0)
Continuous Conversion (SCAN = 1)
ATDDR7
ATDDR6
7 6 5 4 3 2 1 0 ATDDR5
ATDDR4
ATDDR3
Port AD
Result ATDDR2
Register
Interface ATDDR1
ATD Converter ATDDR0
Multiple Channel (MULT = 1)
Single Conversion (SCAN = 0)
ATDDR7
ATDDR6
7 6 5 4 3 2 1 0 ATDDR5
ATDDR4
ATDDR3
Port AD
Result ATDDR2
Register
Interface ATDDR1
ATD Converter ATDDR0
Single Channel (MULT = 1)
Continuous Conversion (SCAN = 1)
ATDDR7
ATDDR6
7 6 5 4 3 2 1 0 ATDDR5
ATDDR4
ATDDR3
Port AD
Result ATDDR2
Register
Interface ATDDR1
ATD Converter ATDDR0
Status Register 0
Pin Description
7 0 Conversion sequence not completed
1 Conversion sequence completed (set to 1 after each
sequence complete when SCAN mode is on)
5 0 No external trigger overrun error has occurred
1 External trigger overrun error has occurred
4 0 No overrun in results
1 A overrun in results
3-0 Conversion Counter (read-only; points to result register that
will receive the result of the current conversion)
Status Register 1
Pin Description
7-0 Conversion complete flag (one bit is set at the end
of every conversion in a conversion sequence,
going from CCF0 in order to CCF7)
0 Conversion # x is not completed
1 Conversion # x is completed and results are
available
Left-Justified Result Register